Terasic ALTERA TR5-F40W, User Manual

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TR5-F40W User
Manual
20 www.terasic.com
June 20, 2018
U10 SFP_REFCLK_p 100.0 MHz HCSL PIN_AF6 10G SFP+
U27 SFP1G_REFCLK_p 125.0 MHz HCSL PIN_AB6 1G SFP+
U27 SATA_REFCLK_p 125.0 MHz HCSL PIN_V6 SATA
U27 HSMC_REFCLK_p 125.0 MHz HCSL PIN_V34 HSMC XCVR
J15 PCIE_REFCLK_p From Host HCSL PIN_AF34 PCI Express
J12 SMA_CLKIN User input 2.5-V PIN_U15
J14 SMA_CLKOUT User output 2.5-V PIN_AD30
Table 2-10 lists the programmable oscillator control pins, signal names, I/O standard and their
corresponding Stratix V GX device pin numbers.
Table 2-10 Programmable oscillator control pin, Signal Name, I/O standard, Pin Assignments
and Descriptions
Programmable
Oscillator
Schematic
Signal Name
I/O Standard
Stratix V GX Pin
Number
Description
Si570
(U10)
CLOCK_SCL 2.5-V PIN_AD15 I2C bus, direct connected
with Si570
CLOCK_SDA 2.5-V PIN_AD16
CDCM61004
(U27)
CLK_RST_n 2.5-V PIN_AC15 Device reset (active low)
CLK_CE 2.5-V PIN_AH15 Chip enable
CLK_PR0 2.5-V PIN_AB16 Output divider control
CLK_PR1 2.5-V PIN_AJ15 Output divider control
CLK_OS0 2.5-V PIN_AG14 Output type select
CLK_OS1 2.5-V PIN_AG15 Output type select
CLK_OD0 2.5-V PIN_AB15 Output divider control
CLK_OD1 2.5-V PIN_AA15 Output divider control
CLK_OD2 2.5-V PIN_AA14 Output divider control
2
2
.
.
6
6
R
R
S
S
4
4
2
2
2
2
S
S
e
e
r
r
i
i
a
a
l
l
P
P
o
o
r
r
t
t
The RS422 is designed to perform communication between boards, allowing a transmission speed
of up to 20 Mbps. Figure 2-11 shows the RS422 block diagram of the development board. The
full-duplex LTC2855 is used to translate the RS422 signal, and the RJ45 is used as an external
connector for the RS422 signal.