TR5-F40W
User
Manual
21
June 20, 2018
Figure 2-11 Block Diagram of RS422
lists the RS422 pin assignments, signal names and functions.
Table 2-11
RS422 Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description
I/O Standard
Stratix V GX Pin
Number
RS422_DE
Driver Enable. A high on DE enables the driver.
A low input will force the driver outputs into a
high impedance state.
2.5-V
PIN_K16
RS422_DIN
Receiver Output. The data is send to FPGA.
PIN_H19
RS422_DOUT
Driver Input. The data is sent from FPGA.
PIN_H17
RS422_RE_n
Receiver Enable. A low enables the receiver. A
high input forces the receiver output into a
high impedance state.
PIN_L16
RS422_TE
Internal Termination Resistance Enable. A high
input will connect a termination resistor (120
Ω
typical)
between pins A and B.
PIN_H16
2
2
.
.
7
7
F
F
L
L
A
A
S
S
H
H
M
M
e
e
m
m
o
o
r
r
y
y
The development board has two 1Gb CFI-compatible synchronous flash devices for non-volatile
storage of FPGA configuration data, user application data, and user code space.
Each interface has a 16-bit data bus and the two devices combined allow for FPP x32 configuration.
This device is part of the shared flash, SSRAM and MAX (FSM) bus, which connects to the flash
