TR5-F40W
User
Manual
29
June 20, 2018
SFPD_TXDISABLE
Turns off and disables the transmitter
output
2.5V
PIN_AT11
SFPD_TXFAULT
Transmitter fault
2.5V
PIN_AR9
2
2
.
.
1
1
0
0
P
P
C
C
I
I
E
E
x
x
p
p
r
r
e
e
s
s
s
s
The FPGA development board is designed to fit entirely into a PC motherboard with x8 or x16 PCI
Express slot. Utilizing built-in transceivers on a Stratix V GX device, it is able to provide a fully
integrated PCI Express-compliant solution for multi-lane (x1, x4, and x8) applications. With the
PCI Express hard IP block incorporated in the Stratix V GX device, it will allow users to implement
simple and fast protocol, as well as saving logic resources for logic application.
presents the pin connection established between the Stratix V GX and PCI Express.
The PCI Express interface supports complete PCI Express Gen1 at 2.5Gbps/lane, Gen2 at
5.0Gbps/lane, and Gen3 at 8.0Gbps/lane protocol stack solution compliant to PCI Express base
specification 3.0 that includes PHY-MAC, Data Link, and transaction layer circuitry embedded in
PCI Express hard IP blocks.
The power of the board can be sourced entirely from the PCI Express edge connector when installed
into a PC motherboard. It is strongly recommended that users connect the PCIe external power
connector to 6-pin 12V DC power connector in the FPGA to avoid FPGA damage due to
insufficient power. The PCIE_REFCLK_p signal is a differential input that is driven from the PC
motherboard on this board through the PCIe edge connector. A DIP switch (SW8) is connected to
the PCI Express to allow different configurations to enable a x1, x4, or x8 PCIe.
summarizes the PCI Express pin assignments of the signal names relative to the Stratix
V GX FPGA.
