Tektronix SPG 422, Service Manual

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Theory of Operation
SPG 422 Service Manual (B034000 and above)
3–23
The microprocessor interface to the Encoder ASIC is essentially done by a bank
of 32 8-bit registers. The Encoder ASIC is mapped into the microprocessor
memory space. Five bits of the external address bus, the external
READ/(WRITE) line, and an address strobe (BLK2) are used to control the
registers. The address strobe, which contains the basic timing information, is
generated whenever the microprocessor accesses those memory locations. The
strobe is used to generate the Encoder ASIC ALE and (CS) signals. The signals
are also decoded and timed by the controller PLD to generate the READ and
WRITE strobes.
Configuration data is written to several of the Encoder ASIC internal registers to
specify the timing offset, standard, etc. The registers also serve as the porthole
through which the segment memories are diagnosed and initialized. At power on,
the configuration data is written to the registers and the segment data is read
from the EPROM and written to the RAM. Subsequent changes to the signals are
just made by changing the configuration data written to the registers.
DAC and Output Filter and Driver.
Finally, the over sampled black signal data is
fed to the output circuitry. The DAC and output section convert the digital
representation of black burst to analog, reconstruct and filter the signal, and
buffer it to drive 75
W
.
Option 2 Board
The Option 2 board produces the additional serial digital test signals that are
available when Option 2 is installed in the SPG 422. the circuitry is identical to
the Bars generation in the standard instrument.
The Test Signal Generator is a complete generator, requiring only a master clock,
(STSGCLK); a synchronous frame reset, (STSS) or (STSR); and some setup
information from the microprocessor. On startup, the processor writes the signal
configuration information to the generator and downloads the necessary audio
and video test signals into RAM.
Horizontal, Vertical, and Field Counters and Decoding PLDs.
U9 and U10 are the
Horizontal, Vertical, and Field Counters and Decoding PLDs.
The clock and reset drive the counter chain. The counter drives state machines
that select the proper test signal RAM address at the correct time in the field.
Timing Reference Signal Generator. U12 is the Timing Reference Signal (TRS)
Generator. It gets the appropriate TRS data addresses and loads them into the
Serial Bars RAMs so that the data is multiplexed into the video signal.
Serial Test Signal
Generation <1>