Tektronix SPG 422, Service Manual

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Theory of Operation
SPG 422 Service Manual (B034000 and above)
3–5
The two Black Burst Generators are nearly identical. The black burst generation
circuit is a complete generator, requiring only a master clock, synchronous frame
PAL and NTSC resets, and setup information from the microprocessor.
The black burst generator incorporates as much of the circuitry as possible into a
large programmable logic device (PLD). The large, random look-up tables are
done in EPROM.
The Black Burst Generator begins with a Frame Reset Generator that takes a
PAL and an NTSC frame reset signal and selects between them, based on the
signal standard chosen. This reset pulse is then delayed by an integer number of
clock cycles specified by the microprocessor. This delayed reset pulse is used to
synchronously reset the horizontal, vertical, and field counters. This program-
mable delay provides the instrument with a way to delay (or advance) the timing
of the generator relative to the master timing source (the genlock). In the case of
the two standard Black Burst Generators, the 27 MHz clock is also delayed in
sub-nanosecond increments, under processor control, before it arrives at the
generator. This allows fine control of output timing.
The clock and reset drive the counter chain. The first counter in the chain is the
horizontal counter, an 11-bit up-counter that counts at 27 MHz and resets itself at
the end of the video line. It is also reset by the frame-reset input. The line length
is specified by the video standard selected. On the last count of the line, the
counter outputs a horizontal carry pulse.
The horizontal segment data is used to divide the horizontal line into a small
number of unique regions. This allows the storage of the actual signal data to be
dramatically compressed.
The second counter in the chain is the vertical counter, a 10-bit up-counter that
runs at 27 MHz. It is enabled to count once per video line by the horizontal carry
pulse. It counts to the end of the frame in the selected video standard and resets
itself. (It is also reset by the frame reset input.) On the last count of the frame,
the counter outputs a vertical carry pulse.
The third counter in the chain is the frame counter, a 2-bit up-counter that runs at
27 MHz. It is enabled to count once per video frame by the horizontal and
vertical carry pulses. It counts to the end of the color frame in the selected video
standard and resets itself. (It is also reset by the frame reset input.)
The counters, horizontal segment decoder, and signal selection bits from the
processor drive the segment decoder PROMs. These PROMs decode the counter
and decoder inputs into pointers to unique blocks of eight samples of black-burst
data.
Signal-segment data PROMs take the segment pointers from the decoder
PROMs and output the 8-bit black-burst data.
The DAC and output circuitry converts the digital representation of black burst
to analog, reconstructs the signal, filters it, and buffers it to drive 75
W
.