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SPG 422 Service Manual (B034000 and above)
3–1
Theory of Operation
This section provides block-level information on how the SPG 422 circuitry
works, for board-level troubleshooting. See Figure 3–1 for an SPG 422 block
diagram. Component-level troubleshooting information is provided later, in a
section titled Detailed Circuit Description.
Genlock
The Genlock input signal enters the circuit on the Output board through the
rear-panel BNC connectors. The signal from the BNC is selected by the 2:1
Multiplexer. The signal then goes to the Sync Stripper that produces a clamped
video signal and a luminance signal for use in the Chroma Filter. The Sync
Stripper uses the output of the Chroma Filter to produce the luma and clamped
video signal. The 2:1 Multiplexer selects the chroma and CW Bypass signals
used as the Color Lock input.
On the Digital board, the outputs of the Sync Lock, Color Lock, Test, and
Internal are put in a 4:1 multiplexer for use as the tune signal for the 13.5 MHz
VCXO. The 13.5 MHz signal is then stepped up in frequency in the 108 MHz
PLL that produces the 108 MHz and 27 MHz clocks. The Genlock Controller
produces the Frame Resets. The Fine Phase circuitry generates delayed versions
of the 27 MHz clock from the 108 MHz clock. The Frame Resets are then
re-synchronized to these delayed clocks. The Fractional Divider uses the 27 MHz
clock to produce the 6.144 MHz clock for the audio signals.
Front Panel Board
The Front Panel board consists of LEDs and switches. The LEDs light on
commands from the CPU. The switches provide control commands to the CPU
that determine the state of the output signals.
The Front Panel Interface converts the X-Y data format of the front-panel
switches into data for the external data bus to control the microprocessor. If the
front panel is disabled, then the commands from the front panel are not
processed.
Summary of Contents for SPG 422
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