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Theory of Operation
3–8
SPG 422 Service Manual (B034000 and above)
Front-Panel LED Drivers.
The microprocessor sends data over the external data
bus, and U14, U15, and U16 convert the commands into driver signals for the
front-panel LEDs, L[0..19].
Display Data Latch.
The Display Data Latch consists of two parts. The first part
gets data from the external data bus and converts it into an analog voltage, U22,
that controls the contrast of the front-panel display. The second part controls the
actual characters displayed on the screen, U17.
The Test Signal Generator is a complete generator, requiring only a master clock,
(SCBCLK); a synchronous frame reset, (SCBFRP) or (SCBFRN); and some
setup information from the microprocessor. On startup, the processor writes the
signal configuration information to the generator and downloads the necessary
audio and video test signals into RAM.
Horizontal, Vertical, and Field Counters and Decoding PLDs.
U25 and U34 are the
Horizontal, Vertical, and Field Counters and Decoding PLDs.
The clocks and reset drive the counter chain. The counter drive state machine
selects the proper test signal RAM address at the correct time in the field.
Timing Reference Signal Generator.
U36 is the Timing Reference Signal (TRS)
Generator. It gets the appropriate TRS data addresses and loads them into the
Serial Bars RAMs so that the data is multiplexed into the video signal.
Serial Bars RAM.
U26 and U27 are the Serial Bars RAM. Each line of the video
signal is stored in sample order, with each video line bottom-justified in memory
on 1 kB boundaries. The required video signals are downloaded into the RAM at
power-up and are not changed during operation unless the video standard is
changed.
The Serial Bars RAMs output, SCBD[0..9], is the parallel video signal with the
TRS data loaded.
Audio Data RAM.
The data in the Audio RAMs is the audio tone in a specific
format for AES audio. This data is read out of the Audio RAMs at a particular
point in the video data stream to be embedded. The audio data is placed into
RAM by the microprocessor by using the address, EA[0..14], and data ED[0..7]
buses and the various control signals.
Serial Digital Coprocessor and Serial Blanker Coprocessor.
The parallel digital
video data with TRS inserted, SCBD[0..9], enters U45. The audio data is then
multiplexed into the data on the data stream from the Audio Data RAMs, U42
Serial Video Generation <3>
Serial Coprocessors <4>
Summary of Contents for SPG 422
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