Teac FD-55 Series, Maintenance Manual

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gate signal against the WRITE GATE input signal.
WRITE GATE input signal
TP2(Erase gate)
(Fig.313) Typical waveform of TP2
Delay FD-55A % F FD-55G
On-delay
200 < \ j 320ys 175 % 210ys
Off-delay 860 % 950ys 500 ^ 550ys
(Table 302) Erase gate delay
(3) TP3 (Phase B)
Test: point to observe the phase B magnetized period of the stepping
motor. For the 48tpi FDD, it is also used for observing the delay
time of the second step pulse which is produced automatically in the
FDD. It is also used for all the FDDs, as the observation point of the
partial 2-phase magnetization timing of the stepping motor.
For the 48tpi FDD, the stepping motor rotates for 2 steps in response
to one STEP input pulse. Therefore, TP3 goes HIGH level for a specified
time when a step-out command from an even track or a step-in command
from an odd track is executed„ Refer to Fig.310.
For the 96tpi FDD, the stepping motor rotates only for 1 step in
response to one STEP input pulse by which one track space is moved.
TP3 maintains HIGH level when the head is on the l+4n(n=0,1,2,-- )
track (phase B magnetized) or for a specified time during step-in or
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