Teac FD-55 Series, Maintenance Manual

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(2) Write circuit
The write circuit consists of write power gate (with side selector),
select gate, data latch, write driver, and erase driver.
The write power gate output (COMO or COMl) becomes high voltage when
the write gate signal or the erase gate signal is TRUE (HIGH level).
These signals are generated by the write/erase gate in the control
circuit when all of the following three conditions are satisfied.
(a) The file protect sensor detects the notch of the disk jacket (write
enable condition).
(b) The WRITE GATE input signal is TRUE.
(c) MX strap is on or the DRIVE SELECT signal is TRUE (LOW).
The write power gate output is supplied to the common terminal of the
head through the diode switch. Table 301 shows the output voltage of
the write power gate in various operations,
Conditions
Write power gate output voltage
COM 0 (for Side 0) COM 1 (for Side 1)
Side 0 write operation High
Low
Side 1 write operation Low High
Side 0 read operation Middle Low
Side 1 read operation Low Middle
High: 10.5V,approx. ' Middle: 4V,approx. Low: 0V,approx.
(Table 301) Write power gate output voltage
The erase gate signal is delayed appropriately against the write gate
signal. Since the erase gap is about 0.85mm (FD-55A ^ F models) or
0.585mm (FD-55G model) behind the read/write gap, it is necessary for
the erase driver to delay the write gate signal so that the written
data is completely trimmed by the erase head (tunnel erase). The
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