1.1. Introduction
.
n
One set of time capture registers is used for event time capture. Time is captured on the rising or
falling edge (user programmable) of the Event Input signal provided to the TFP via the J1 I/O con-
nector or from the Programmable Periodic Output signal. The Event Input configuration is manip-
ulated via the CONTROL Register as described in "CONTROL Register (0x10)" on page 28.
n
Two sets of event capture registers are available from dual-purposed input pins. J1 pin 10 may be
used as the DCLS Time Code Input or as the Event2 input. J1 pin 14 may be used as the Exter-
nal 1PPS Input or as the Event3 input.
n
Seven maskable interrupt sources are supported. All interrupt sources may be polled. Interrupts
are discussed in more detail in "MASK Register (0x18)" on page 31.
Note: The bc635PCI-V2 and bc637PCI-V2 do not provide interrupts at system start-up and therefore
do not support the PCI Local Bus Specification Revision 2.3 feature of software disable of interrupts
at start-up.
1.1.4. Specifications and Settings
Time Code Inputs
Formats
IRIG A, B, G, E, IEEE 1344
1
, NASA 36, XR3 and 2137 (AM/DCLS)
Carrier Range
± 5 PPM
Time Accuracy
2
< 5 μsec. (AM with carrier frequencies 1 kHz or greater)
< 1 μsec. (DCLS)
AM Modulation Ratio
2:1 to 4:1
AM Input Amplitude
1 to 8 Vp-p
AM Input Impedance
5 kΩ, AC Coupled
DCLS Input
5V HCMOS, >2V high, <0.8V low
1
IEEE 1344 compliance - The translator processes the 27 control function bits of IRIG B time code
as set forth in IEEE 1344.
2
May require a calibration to attain this accuracy. See "1.3.7. AM Time Code Calibration" on page 21.
Time Code Outputs
Formats
IRIG A, B, G, E, IEEE 1344, NASA 36, XR3 & 2137 (Modulated/DCLS)
Modulation Ratio
3:1 ± 10%
Output Amplitude
3V p-p ±10% (fixed) into 50 Ω
DC Level Shift
5V HCMOS, >2V high, < 0.8V low into 50 Ω
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