Stanford Research Systems SR865A, Operation Manual

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Appendix G Performance Tests 185
SR865A DSP Lock-in Amplifier
Common Mode Rejection
This test measures the common mode rejection of the voltage input.
Setup
We will use the internal oscillator sine output to provide the signal.
Connect the Sine Out+ to both the A and B inputs of the lock-in. Use equal length cables from A and B to
a BNC TEE. Connect the cable from the Sine Out+ to the TEE. This test only uses ONE Sine Out BNC.
Do not use any termination.
Procedure
1) {PRESET} (press [Save Recall], then touch {Recall default}. Touch {Confirm})
2) Use the front panel to make the following adjustments
Touch {Fint} to display the internal frequency keypad
Enter a frequency of 1.0 kHz.
Touch {Ampl} to display the sine out amplitude keypad
Enter an amplitude of 1.0 V.
3) The value of R (yellow) should be 1.000 V (within 2%).
4) Use the front panel to make the following adjustments
Press [Couple]
Select DC coupling.
Press [A − B]
Select A
−
B.
Press [Sensitivity Down] multiple times
Set the sensitivity to 200 μV.
5) Record the value of R (yellow).
6) This completes the CMRR measurement test. The common mode rejection is 20log(1.0/R) where
R is in Volts. Enter the results of this test in the test record at the end of this section.