Stanford Research Systems SR865A, Operation Manual

Page: 120 / 221

102 Programming Chapter 4
SR865A DSP Lock-in Amplifier
GPIB Interface Ready And Status
The Interface Ready bit (bit 1) in the Serial Poll Status Byte signals that the SR865A is
ready to receive and execute a command. When a command is received, this bit is cleared
indicating that an operation is in progress. While the operation is in progress, no other
commands will be received. Only GPIB serial polling will generate a response while a
command is in progress. When the command execution terminates, the Interface Ready
bit is set again and new commands can be received. Since most commands execute very
quickly, the host computer does not need to continually check the Interface Ready bit.
When using the GPIB interface, serial polling may be used to check the Interface Ready
bit in the Serial Poll Byte while an operation is in progress. After the Interface Ready bit
becomes set, signaling the completion of the command, then the ERR or ESB bit may be
checked to verify successful completion of the command.
If an interface other than GPIB is used, then serial polling is not available. The STB? ,
ESR? , ERRS? , and LIAS? status query commands may be used to query the Status
Bytes. Since the SR865A processes one command at a time, the status query will not be
processed until the previous operation is finished. Thus a response to the status query in
itself signals that the previous command is finished. The query response may then be
checked for various errors.