viii Specifications
SR865A DSP Lock-in Amplifier
Sine Output
Outputs Differential
or
Single-ended
Output Impedance
50
Ω
source
Amplitude
1 nVrms to 2 Vrms (specified amplitude is differential into 50
Ω
loads)
Output amplitude is halved when used single-ended
Output amplitude is doubled into a high impedance load
Amplitude Resolution
3 digits or 1 nV, whichever is greater
dc Offset
±5 V, differential or common mode
Offset Resolution
3 digits or 0.1 mV, whichever is greater
Output Limit
±6 V, sum of dc offset and peak amplitude
Sync
Logic level sync on rear panel (via BlazeX output)
Data
Data Channels
4 data channels are displayed and graphed (green, blue, yellow, orange)
Data Sources
Each data channel can be assigned any of these data sources
:
X, Y, R,
θ
, Aux In 1–4, Aux Out 1–2, X
noise
, Y
noise
, Sine Out Amplitude, Sine Out
DC Level, reference phase, f
int
or f
ext
Data History
All data sources are continuously stored at all chart display time scales.
The complete stored history of any data source can be displayed at any time.
Offset
X, Y and R may be offset up to ±999% of the sensitivity
Ratio
X, and Y may be ratioed by Aux In 3; R may be ratioed by Aux In 4
Expand
X, Y and R may be expanded by ×10 or ×100
Capture Buffer
1 Mpoints internal data storage. Store (X), (X and Y), (R and
θ
) or (X, Y, R and
θ
)
at sample rates up to 1.25 MHz. This is in addition to the data histories for the
chart display.
Data Streaming
Realtime streaming of data, either (X), (X and Y), (R and
θ
) or (X, Y, R and
θ
) at
sample rates up to 1.25 MHz over Ethernet interface
Scanning
One of the following parameters may be scanned
:
f
int
, Sine Out Amplitude, Sine Out DC Level, Aux Out 1 or 2.
FFT
Source
Input ADC, demodulator output, or filter output
Record length
1024 bins
Averaging exponential
rms
Inputs and Outputs
CH 1 Output
Proportional to X or R, ±10 V full scale thru 50
Ω
CH 2 Output
Proportional to Y or
θ
, ±10 V full scale thru 50
Ω
X and Y Outputs
Proportional to X and Y, ±10 V full scale thru 50
Ω
, rear panel
BlazeX
Low latency output of X, ±2.0 V full scale or
logic level reference sync output, either thru 50
Ω
Aux Outputs
4 BNC D/A outputs, ±10.5 V thru 50
Ω
, 1 mV resolution
Aux Inputs
4 BNC A/D inputs, ±10.5 V, 1 mV resolution, 1 M
Ω
input
Trigger Input
TTL input triggers storage into the internal capture buffer
Monitor Output
Analog output of the signal amplifier
HDMI
Video output to external monitor or TV, 640x480/60 Hz.
Timebase Input/Output
1 Vrms 10 MHz clock to synchronize internal reference frequency to other units
Summary of Contents for SR865A
Page 5: ...Safety and Preparation For Use iii SR865A DSP Lock in Amplifier...
Page 6: ...iv Safety and Preparation For Use SR865A DSP Lock in Amplifier...
Page 54: ...36 Getting Started Chapter 1 SR865A DSP Lock in Amplifier...
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Page 186: ...168 The FFT Display Appendix B SR865A DSP Lock in Amplifier...
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