SST SST-ASI-SLC, User Manual

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M0 and M1 Files
59
Monitoring Bit Addresses
M0 and M1 Bit Monitoring Disabled
When you monitor a ladder program in run or test mode, the following bit
instructions, addressed to an M0 or M1 file, are indicated as false regardless
of their actual true/false logical state.
--| |-- --|/|-- --( )-- --(L)-- --(U)--
M0 and M1 Bit Monitoring Enabled
The SLC 5/03, SLC 5/04 and SLC 5/05 processors allow you to monitor the
actual state of each addressed M0/M1 address (or data table). The
highlighting appears normal when compared with the other processor data
files. The SLC 5/03’s performance will be degraded to the degree of M0/M1
referenced screen data.
If you need to show the state of the M0 or M1 addressed bit, you can transfer
the state to an internal processor bit.
Transferring Data Between Processor Files and M0/M1 Files
The SLC processor does not contain an image of the M0 or M1 file. As a
result, you must edit and monitor M0 and M1 file data via instructions in your
ladder program. For example, you can copy a block of data from a processor
data file to an M0 or M1 data file or vice versa using the COP instruction in
your ladder program.
Access Time
During the program scan, the SLC processor must access the scanner card to
read or write M0 or M1 data. This access time must be added to the execution
time of each instruction referencing M0 or M1 data. The
SLC 500 Instruction
Set Reference Manual contains details about this access time.
Minimizing the SLC Scan Time
You can keep the SLC processor scan time at a minimum by minimizing the
use of instructions that address M0 or M1 files.