Sony UWP-V1, Service Manual

Page: 139 / 164

4-9
UWP Series
4-9
URX-P2 URX-P2
Circuit Description
URX-P2
URX-P2 consists of the following four blocks.
1.
RF block
2. AF block
3. Power block
4. CPU block
The respective blocks have the following functions.
1. RF block
The RF block consists of the six circuits as shown below.
(1) RF amplifier circuit
The RF inputs as many as the number of antennas “a” and
“b” are provided.
The RF signal from which the desired frequency band
width is selected by the band-pass filter (antenna a =
FL201, antenna b = FL101) is amplified by the RF amplifi-
er (antenna a = Q201, antenna b = Q101). The amplified
RF signal passes through another band-pass filter (antenna
a = FL221, antenna b = FL121) and attenuator (R120,
R129, R130), and is input to the 1st mixer circuit shown as
(2). Gain of the RF amplifier block is about 10 dB includ-
ing the loss due to the band-pass filters.
(2) 1st mixer circuit and 1st IF amplifier circuit
The signal that is amplified by the RF amplifier is mixed
with the 1st local oscillator output signal shown as (3) by
the 1st mixer circuit (antenna a = Q221/Q222 antenna b =
Q121/Q122). Desired frequency band is selected from the
mixed signal by the SAW filter (antenna a = FL221,
antenna b = FL121) and is output to the (4) 2nd mixer
circuit as the 1st IF signal. Frequency of the 1st IF signal is
243.95 MHz.
(3) 1st local oscillator circuit
The 1st local oscillator signal is generated by VCO
(CP301), buffered by the amplifier (antenna a = Q211,
antenna b = Q111) and mixed with the RF signal by the (2)
1st mixer circuit. The VCO (CP301) is controlled by the
PLL IC (IC321) and CPU (IC601).
(4) 2nd mixer circuit and 2nd IF amplifier circuit
The 1st IF signal is mixed with the (5) 2nd local oscillator
by the 2nd mixer circuit (antenna a = Q241/Q242, antenna
b = Q141/Q142). Desired frequency band is selected from
the mixed signal by the ceramic filter (antenna a = CF241,
antenna b = CF141) and is output to the (6) 2nd IF circuit
as the 2nd IF signal. Frequency of the 2nd IF signal is 10.7
MHz.
(5) 2nd local oscillator circuit
The 2nd local oscillator signal is generated by the oscilla-
tor circuit consisting of the transistors (Q341 and Q342),
buffered by the amplifier (antenna a = Q231, antenna b =
Q131) and mixed with the 1st IF signal by the (4) 2nd
mixer circuit. Frequency of the 2nd local oscillator signal
is 233.25 MHz, and is kept constant by controlling the
voltage applied to VARI cap diode (D341) with the PLL
IC (IC321).
(6) 2nd IF circuit
The 2nd IF signal that is output from the (4) 2nd mixer
circuit is amplified by the transistor (antenna a = Q107,
antenna b = Q207) and the 2nd IF amplifier IC (antenna a
= IC261, antenna b = IC161). Desired frequency band of
the 2nd IF signal is selected by the ceramic filter (antenna
a = CF251/CF261 antenna b = CF151/CF161).
At the same time, it outputs the DC voltage that changes its
level depending on the RF input signal level, as the RSSI
signal. The RSSI signal is used to select the diversity and
to control squelch (muting). The 2nd IF signal that is
amplified by the above amplifier is detected by the detector
IC (antenna a = IC271, antenna b = IC171) and the ceramic
discriminator (antenna a = CF271, antenna b = CF171),
and is output as the audio signal.
2. AF block
The audio signal (two channels from antennas “a” and “b”)
that has passed through the high-frequency block and is
amplified by the OP amplifier (IC181) is input to the
diversity circuit (IC401). The diversity circuit is controlled
by the CPU (IC601) in accordance with the RSSI signal
that is generated by the 2nd IF amplifier IC of the high-
frequency block. Output signal from the diversity circuit
takes the two signal paths: One output is connected to the
(1) squelch (muting) circuit. The other output is connected
to the (4) TONE detector circuit and the (5) noise detector
circuit via the buffer amplifier (IC441-1/2)
(1) Squelch circuit
The squelch circuit (IC401) is controlled by the CPU
(IC601) in accordance with the RSSI signal the tone and
the noise detector output.
The audio output signal from the squelch (muting) circuit
enters the de-emphasis circuit (IC411-1/2) having time
constant 50
u s and the low-pass filter circuit (IC411-2/2)
having the cut-off frequency of 25 kHz. It then enters the
expander circuit (IC421). The audio output signal from the
expander is buffered by the buffer Amplifier (IC422-1/2)
having the waiting time of 150
u s and takes the two signal
paths. One output signal is the main audio output signal
that is output from the output connector (AF OUT) via the
muting circuit (Q431, Q432) that suppresses the noise at
the instance of power ON/OFF. The other output is
connected to the (2) MONITOR output circuit and the (3)
AF level detector circuit.
(2) MONITOR output circuit
One of the audio signals from the main audio output signal
is buffered by buffer amplifier (IC422-2/2) and passes
through the level-control analog switch (IC461, IC471)
and enters the monitor amplifier (IC481) from which the
audio output signal is connected to the HEADPHONES
connector. The audio monitor level is adjusted by the
analog switch IC (IC461, IC471) that is controlled by the
CPU (IC601) as the “
+
” or “
_
” button is operated.
(3) AF level detector circuit
The other output of the audio signals from the main audio
output signal is amplified by amplifier (IC451-2/2) and
enters the rectifier circuit (D451). The output voltage that
is developed by the rectifier circuit is detected by the CPU
(IC601). Output signal of the detector is used to indicate
the AF signal level on the LCD.
(4) TONE detector circuit
The audio output signal from the diversity circuit (IC401-
1/3) is amplified by amplifier (IC441-2/2) containing a
filter consisting of crystal oscillator (X441, X442) and
enters the rectifier (D441). Output voltage from the
rectifier is detected by the CPU (IC601). Output signal
from the detector is used to control the (1) squelch circuit.
(5) Noise detector circuit
The audio output signal from the diversity circuit (IC401-
1/3) passes through the amplifier (IC451-1/2) containing
the high-pass filter having cut-off frequency 87 kHz and
enters the rectifier circuit (D452). Output voltage from the
rectifier is detected by the CPU (IC601). Output signal
from the detector is used to control the (1) squelch circuit.
3. Power block
The power bock consists of the following two circuits.
(1) POWER switch circuit
When the POWER switch (S11) is pressed to ON, the Tr
switch (Q13) is turned on so that the power voltage is
supplied to the DC-DC converter circuit.
(2) DC-DC converter circuit
The voltage supplied from the POWER switch circuit is
converted to the
+ 3.3 V power by the control IC (IC11)
and the switching FET (Q11).
4. CPU block
The CPU (IC601) performs the following controls.
(1) LCD display
. Reception channel or reception frequency indication
. Blank channel search control
.
AUTO POWER SAVE control
.
Audio output level indication
. Battery power consumption indication
. RF input level indication
.
Accumulated operating hours indication
.
Error message indication
(2) LED display
.
RF input level indication
The RF input level is indicated on the LED (D641) using
the RSSI signal. The green LED is used. The OR-logic
output of the RSSI signals from the antennas “a” and “b”
is indicated.
.
Squelch (muting) control
Muting of the audio signal is performed by detecting the
RSSI signal, the TONE signal and noise signal.
.
PLL control
CPU (IC601) controls the PLL IC (IC321) using the
frequency data stored in the EEPROM (IC671).
. MONITOR level control
The MONITOR level is adjusted by controlling the
analog switch IC (IC461, IC471) in accordance with the
“
+ ” and “ _ ” button operations.
. Clock oscillator circuit
The clock signal (frequency is 8 MHz) is oscillated by
the crystal oscillator (X621) and IC621. This clock
signal is used by the CPU (IC601) and the PLL IC
(IC321).
(3) AUTO POWER SAVE function
If the RF signal that is transmitted from the transmitter
cannot be received by the receiver, and when other require-
ments are satisfied, the power supply to the antenna “b”
circuitry is shut down by the CPU that controls Q351.
Thus, the consumption current can be reduced making
contribution in extending battery operating hours. As soon
as the antenna “a” receives the RF signal from transmitter,
this function is canceled.