Sony UWP-V1, Service Manual

Page: 137 / 164

4-7
UWP Series
4-7
URX-M2 URX-M2
Circuit Description
URX-M2 consists of the MB-1129 board and the DP-456
board. URX-M2 can be divided into the following four
blocks.
1. RF block
2. AF block
3. Power block
4. CPU block
The respective blocks have the following functions.
1. RF block
The RF block consists of the six circuits as shown below.
(1) RF amplifier
The RF input signals are supplied from the antennas “a”
and “b” separately. The RF input signal of the desired
frequency bandwidth is selected by the band-pass filter
(antenna a = FT101, antenna b = FT201), and is amplified
by the RF amplifier (antenna a = Q101, antenna b = Q201).
The amplified RF signal passes through another band-pass
filter (antenna a = FT102, antenna b = FT202) and is input
to the 1st mixer circuit described in the next paragraph (2).
Gain of the RF amplifier is approximately 10 dB including
the loss due to the band-pass filters.
(2) 1st mixer circuit
The input signal that is amplified by the RF amplifier is
mixed with the output signal from the 1st local oscillator
described in the next paragraph (3), by the 1st mixer circuit
(antenna a = Q103/Q104, antenna b = Q203/Q204). The
mixed signal is sent to the SAW filter (antenna a =
SWF101, antenna b = SWF201) where only the desired
frequency bandwidth is selected. The output from the 1st
mixer is sent to the 2nd mixer described in the next
paragraph (4) as the 1st IF signal. Frequency of the 1st IF
signal is 243.95 MHz.
(3) 1st local oscillator
The 1st local oscillator signal is generated by VCO
(X301), buffered by the amplifier (antenna a = Q102,
antenna b = Q202) and mixed with the RF signal by the 1st
mixer circuit as described in the previous paragraph (2).
VCO (X301) is controlled by the PLL IC (IC301) and CPU
(IC505).
(4) 2nd mixer
The 1st IF signal is mixed with the output signal from the
2nd local oscillator that is described in the next paragraph
(5) by the 2nd mixer circuit (antenna a = Q105/Q106,
antenna b = Q205/Q206). The mixed signal is sent to the
ceramic filter (antenna a = CF101, antenna b = CF201)
where only the desired frequency bandwidth is selected.
The output signal from the ceramic filter is sent to the 2nd
IF amplifier as the 2nd IF signal as described in the
subsequent paragraph (6). Frequency of the 2nd IF signal
is 10.7 MHz.
(5) 2nd local oscillator
The 2nd local oscillator signal is generated by the oscilla-
tor circuit consisting of the transistors (Q305/Q306),
buffered by the amplifier (antenna a = Q301, antenna b =
Q302) and mixed with the 1st IF signal by the 2nd mixer
circuit as described in paragraph (4). Frequency of the 2nd
local oscillator signal is 233.25 MHz, and is maintained to
a constant frequency by controlling the DC voltage to be
applied to the VARY cap diode (D301) with the PLL IC
(IC301).
(6) 2nd IF amplifier
The 2nd IF signal that is output from the 2nd mixer
described in (4) is amplified by the transistor (antenna a =
Q107, antenna b = Q207) and by the 2nd IF amplifier IC
(antenna a = IC101, antenna b = IC201). The 2nd IF signal
is sent to the ceramic filter (antenna a = CFT102/CF103,
antenna b = CF202/CF203) where only the desired fre-
quency bandwidth is selected. At the same time, the 2nd IF
amplifier IC outputs the DC voltage that changes its level
in accordance with the level of the RF input signal as the
RSSI signal. Based on the RSSI signal level, the diversity
is selected and the squelch is controlled. The 2nd IF signal
that is amplified by the above amplifier is detected by the
detector IC (antenna a = IC102, antenna b = IC202) and by
the ceramic discriminator (antenna a = CF104, antenna b =
CF204), and is output as the audio signal.
2. AF block
The audio signal (of two channels from antennas "a" and
"b" respectively) that has passed through the RF block and
is amplified by the OP amplifier (IC401) is input to the
diversity circuit (IC403-1/3). The diversity circuit is
controlled by the CPU (IC505) by comparing the RSSI
signal of antenna “a” with that of antenna “b” to select
whichever the larger, whereas the RSSI signals are gener-
ated by the 2nd IF amplifier IC of the RF block. Output
signal from the diversity circuit takes the two signal paths:
One output signal is sent to the (1) squelch circuit. The
other output signal is sent to the (3) TONE detector circuit
and the (4) noise detector circuit via the buffer (IC406-1/
2).
(1) Squelch circuit
The squelch circuit (IC403-2/3) is controlled by the CPU
(IC505) in accordance with the RSSI signal, the output
signal from the TONE detector circuit (3) and the output
signal from the noise detector circuit (4). The audio signal
that is output from the squelch circuit enters the de-
emphasis circuit (IC404-1/2) having time constant 50
u s
and the low-pass filter (IC404-2/2) having the cut-off
frequency of 25 kHz. The low-pass filter output signal then
enters the expander circuit (IC402). The audio output
signal from the expander is buffered by the buffer amplifi-
er (IC405-1/2) having the waiting time of 150
u s and takes
the two signal paths. One output signal becomes the main
audio output signal from the unit. The other output signal
is sent to the (2) AF level detector circuit.
(2) AF level detector circuit
A part of the main audio output signal is sent to the voltage
follower (IC405-2/2), amplified by the amplifier (IC407-2/
2) and enters the rectifier (D401). Output voltage that is
developed by the rectifier is detected by CPU (IC505).
Output signal of the detector is used to indicate the AF
signal level on the LCD.
(3) TONE detector circuit
The audio signal that is output from the diversity circuit
(IC403-1/3) is amplified by amplifier (IC406-2/2) contain-
ing a filter consisting of crystal oscillators (X401 and
X402) and enters the rectifier (D402). Output voltage that
is developed by the rectifier is detected by CPU (IC505).
Output signal from the detector is used to control the (1)
squelch circuit.
(4) Noise detector circuit
The audio output signal from the diversity circuit (IC403-
1/3) passes through the amplifier (IC407-1/2) containing
the high-pass filter having cut-off frequency 87 kHz and
enters the rectifier circuit (D403). Output voltage that is
developed by the rectifier is detected by CPU (IC505).
Output signal from the detector is used to control the (1)
squelch circuit.
3. Power block
The 9 V input power that is supplied from an external
power source is converted of its voltage from 9 V to 6 V
by the DC/DC converter (IC302), and is at the same time
converted to 3.3 V power voltage by the regulator IC
(IC303). The original 9 V power as it is supplied from
external power source without power regulation is used to
drive the latter circuit of the audio output circuit. The
regulated 6 V power is used by the RF circuit, the front
stage of the audio circuit and by the detector circuit. The
regulated 3.3 V power is used by all circuits other than the
above circuits.
4. CPU block
The CPU (IC505) performs the following controls.
(1) LCD display
. Reception channel indication or reception frequency
indication
.
Audio output level indication
. Between the RF input signal of antenna “a” and that of
antenna “b”, only the RF input signal having the larger
RSSI signal is indicated of its level in four levels.
.
Error message indication
(2) LED display
.
RF input level indication
When the RSSI signal exceeds the squelch level, the RF
input signal level is indicated. The green LED is used.
(3) Squelch control
Muting of the audio signal is switched ON/OFF by the
judgment from the RSSI signal, the tone signal and the
noise signal amplitude.
(4) PLL control
CPU (IC505) controls the PLL IC (IC301) using the
frequency data stored in the EEPROM (IC502).
(5) Clock oscillator
The clock signal (frequency of which is 4 MHz) is
oscillated by the crystal oscillator (X501) and the
oscillator circuit inside the CPU. This clock signal is
used by the CPU (IC505) and the PLL IC (IC301).