Sony PCS-1500, Service Manual

Page: 110 / 198

3-20
PCS-1500/1500P
OD
7-0
OAD
2-0
\CS
\ORD
\OWE
A
14-0
\ROMCS
D
7-0
\RD
LTA
\HCS_BRI
\INT_BRI
I-Interface Controller(IC800)
HD81504RFE
15
HA1-3
\HRD
\HWR
HD0-7
256Kbit SRAM(IC802)
8
8
3
from/to
CPU BLOCK
\RAMCS
\WR
CK8K
CK64K
TBA
TBB
RBB
RBA
LTB
LRB
LRA
\CE
A
0-13
I/O
0-7
\WE
\OE
\CE
A
0-14
I/O
0-7
\WE
\OE
256Kbit SRAM(IC801)
TEST0
15
8
\OE
\OC
CLK
D Q
A
12,13
Status Latch Block
(IC806,805,803)
EXTAL
\RESET
DIR
\G
Transceiver(IC810)
Buffer(IC811)
Latch(IC808,809)
\WDT
SDET
\INT
CHK
2
CLK_L,H
\OE
\DOE
\RAM
\81504
\SDETCLR
\STAT
HA4,5
\MODESET
\DOWNLOAD
2
MODE_SET
\HDEN
DIR
from
CPU BLOCK
from
NETIF BLOCK(IC750)
from
CPU BLOCK
CK12M
\RES_BRI
from
CPU BLOCK
Host Bus Decoder Block
(IC804,803,807,812)
\G
NTSC/PAL
\CAM_LOCK
from CN910
HD0
HD2
HD4
HD7
T202
T201
from CN800
to CN800
FL800
8
8
from
NETIF BLOCK(IC750)
from
NETIF BLOCK(IC750)
to/from
NETIF BLOCK
(IC750)
to
NETIF BLOCK
(IC750)
Buffer(IC758)
Fig. 3-11 BRI Block
3-2. Circuit Description of the Respective Boards