Sony MCE-K700, Service Manual

Page: 41 / 66

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• IC507 MPEG DECODER (CXD1852Q)/VIDEO board
Pin Name
V
SS
XTL0O
XTL0I
V
DD
HA2
HA3
HD0
HD1
HD2
HD3
HD4
HD5
HD6
V
DD
V
SS
HD7
MA3
MA4
MA2
MA5
MA1
V
SS
MA6
MA0
BC
TCKI
TDI
TENAI
TDO
VST
V
SS
MA7
MA8
XRAS
XMWE
XCAS2
/MA9
XCAS0
MD7
MD8
MD6
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
–
O
I
–
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
–
I/O
O
O
O
O
O
–
O
O
I
I
I
I
I
I
–
O
O
O
O
O
O
I/O
I/O
I/O
Function
Ground
Video decoder master clock pin. Input the XTL0I clock or connect an oscillator between
XTL0I and XTL0O. The recommended frequencies are 27MHz, 28.6363MHz (NTSC 8fsc),
and 35.4686 MHz (PAL 8fsc).
+5V power supply
Address input pin. In some cases, serves as the control signal and data input according to
the setting of the control mode.
Data input/output
+5V power supply
Ground
Data input/output
Address signal pin. Connect to the DRAM address pin with the same number.
Ground
Address signal pin. Connect to the DRAM address pin with the same number.
For test
For test (Connect to ground)
Ground
Address signal pin. Connect to the DRAM address pin with the same number.
RAS signal pin. Connect to the RAS pin of the DRAM. Same for the 256Kw
×
16b, 256Kw
×
16b
×
2, and 512Kw
×
8b
×
2 DRAM structures.
WE signal pin. Connect to the WE pin of the DRAM.
CAS signal. Connect to the CAS pin of the DRAM so as to control the lower bytes of the
upper word (256K to 512K-1) for the 256Kw
×
16b
×
2 DRAM structure. / Address signal
pin. Connect to the DRAM address pin with the same number.
CAS signal. Connect to the CAS pin of the DRAM so as to control the lower bytes (MD0 to
MD7) for 256Kw
×
16b and 512Kw
×
8b
×
2 DRAM structures, and to control the lower
bytes of the lower word (0 to 256K-1) for the 256Kw
×
16b
×
2 DRAM structure.
Data input/output signal pin. Connect to the DRAM data pin so that the lower and upper
bytes of the data correspond to the CAS0 to CAS3 controls.