— 59 —
Pin Name
AVD4
N.C
AVS4
N.C
AOUT1
AVS1
AIN1
N.C
LO1
AVD1
N.C
VDD2
VSS3
N.C
VSS4
VDD3
N.C
VSS5
VDD4
N.C
VSS6
VDD5
TST0
TST1
TST2
TST3
VSS7
XS24
SO
SI
BCK
LRCK
XMST
VSS8
VDD6
SCK
READY
TRDT
Pin No.
41
42
43
44
45
46
47
48
49
50
51-52
53
54
55-64
65
66
67-75
76
77
78-82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
–
–
–
–
O
–
I
–
I
–
–
–
–
–
–
–
–
–
–
–
–
–
I
I
I
I
–
I
O
I
I/O
I/O
I
–
–
I
O
O
Function
Power supply for CH-1 • DA converter
Normally open
Ground for CH-1 • DA converter
Normally open
CH-1 • DA converter • LPF output (Not used. open)
Ground for CH-1 • AD converter
CH-1 • AD converter analog
Normally open
CH-1 • AD converter analog input. Op amplifier inverter output
Power supply for CH-1 • AD converter
Normally open
Digital block power supply
Digital block ground
Normally open
Digital block ground
Digital block power supply
Normaly open
Digital block ground
Digital block power supply
Normally open
Digital block ground
Digital block power supply
Test pin. Normally fixed at “L” (Connected to ground)
Test pin. Normally fixed at “L” (Connected to ground)
Test pin. Normally fixed at “L” (Connected to ground)
Test pin. Normally fixed at “L” (Connected to ground)
Digital block ground
24/32 bit slot selecting of serial data “L”: 24 bit slot (Available in the slave mode)
(Connected to ground)
One sampling two channel serial data output (Not used. Open)
One sampling two channel serial data input (Not used. Open)
Serial bit transfer clock pin of serial input/output data SI and SO
Sampling frequency clock pin of serial input/output data SI and SO
Mater/slave mode switching input of BCK and LRCK. “L”: master mode
(Connected to +5V)
Digital block ground
Digital block power supply
Shift clock input from system controller (CXP82532-010Q)
Transfer eneble signal output of system controller (CXP82532-010Q). “L”: Inhibit transfer.
Serial data output to system controller (CXP82532-010Q)
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