4-29
HVR-Z5C/Z5E/Z5J/Z5N/Z5P/Z5U
N O M A R K : R E C / P B M O D E
2 . 8
0
2 . 8
2 . 1
2 . 1
2 . 8
0
2 . 8
2 . 8
CAM_SI
C A M _ S C K
P _ D R I V E _ B
Y _ D R I V E _ B
D S C K _ V M
XCS_SIO_CAM
Y _ D R I V E _ A
C A M _ S O
X R S T _ I C _ 7 0 0 1 _ C P U
X C S _ S I O _ C A M
C A M _ S I
CAM_SO
C A M _ V D
P _ D R I V E _ A
C A M _ V D
C A M _ S C K
P _ D R I V E _ A
P _ D R I V E _ B
Y _ D R I V E _ A
Y _ D R I V E _ B
DSCK_VM
R E G _ G N D
R 7 0 3 7
X X
R 7 0 2 3
X X
R 7 0 3 5
1 0 0 k
C 7 0 0 8
0 . 0 1 u
R 7 0 0 9
3 3 k
R 7 0 2 7
X X
C L 7 0 0 1
C 7 0 0 3
0 . 1 u
Y A W _ A D _ I C _ 7 0 0 1
R7019 27k
R 7 0 1 0
2 7 k
Y _ D R I V E _ B
R 7 0 1 8
3 3 k
D _ 2 . 8 V
C 7 0 1 2
X X
R 7 0 0 3
X X
R 7 0 2 4
0
R 7 0 1 1
2 7 k
D _ 1 . 5 V
R7020
27k
C 7 0 1 3
X X
R 7 0 2 2
8 2 0 0
A _ 2 . 8 V _ R E G
C 7 0 1 5
2 2 u
4 V
C 7 0 1 1
X X
R 7 0 0 6
X X
D S C K _ V M
R E G _ G N D
R 7 0 0 5
1 8 k
R E G _ G N D
CL7002
X R S T _ I C _ 7 0 0 1 _ C P U
C 7 0 0 7
X X
Y _ D R I V E _ A
L E N S _ 5 V
R7015
XX
R 7 0 2 6
0
C 7 0 1 0
X X
C 7 0 1 6
0 . 1 u
R E G _ G N D
R 7 0 0 8
0
R 7 0 1 7
0
P I T C H _ A D _ I C _ 7 0 0 1
C 7 0 0 6
1 u
R 7 0 1 3
X X
P _ D R I V E _ A
C 7 0 1 4
X X
R 7 0 0 1
X X
P _ D R I V E _ B
C 7 0 0 2
1 u
I C 7 0 0 1
R 2 J 3 0 5 0 0 L G
C1
V M 5 _ 0
C10
V M 5 _ 1
A1
P G N D
E1
P G N D
A10
P G N D
E10
P G N D
F1
D V C C
F10
D G N D
D1
O U T 0 A
B1
O U T 0 B
D10
O U T 1 A
B10
O U T 1 B
E2
M D _ I N 0
F2
M D _ B R 0
G2
M D _ E N 0
E9
M D _ I N 1
F9
M D _ B R 1
G9
M D _ E N 1
G7
x M D _ P S
VCCA3
K 1
VCCA3
K 6
GNDA3
K 7
GNDA3
K 1 0
OP_IP0
H 2
OP_OUT0
J 1
OP_IN0
H 1
DA0
K 2
IA0
J 2
IB0
K 3
OP_OUT2
J 3
OP_IN2
J 4
OP_IP1
J 9
OP_OUT1
J 1 0
OP_IN1
H 9
DA1
K 9
IA1
J 8
IB1
K 8
C H 0
K4
C H 1
G5
C H 2
K5
C H 3
J5
V B
J6
P W M 2
D4
P W M 3
D7
U D I D E B U G
F7
U D I T R S T
E7
U D I T C K
G1
U T I T M S
F4
U D I T D O
G10
U D I T D I
E4
V D
C9
P I O 3
B9
P I O 2
B8
P I O 1
B7
XSCS
A 5
SO
B 4
SI
A 4
CLK
A 3
RESET_N
A 7
VCCD3
A 2
VCCD3
A 9
GNDD3
A 8
VCCD15
D 2
VCCD15
D 9
GNDD15
H 1 0
TEST1
B 3
TEST2
B 2
TEST3
C 2
MARK
E 5
CPU_PIO_0
D 5
CPU_PIO_1
D 6
G4
T E S T
OP_OUT3
G 6
OP_IN3
J 7
P I O 0
B6
X D L
A6
S C K
B5
C 7 0 0 1
2 2 u
1 0 V
R 7 0 0 2
X X
R 7 0 0 4
0
R 7 0 3 6
X X
R 7 0 1 2
8 2 0 0
C 7 0 0 4
0 . 0 1 u
R 7 0 0 7
1 0 k
R 7 0 1 4
1 8 k
C7009 0.01u
R7016
10k
R 7 0 3 0
1 0 0 k
R 7 0 3 1
1 0 0 k
R 7 0 3 2
1 0 0 k
R 7 0 3 3
1 0 0 k
R 7 0 3 4
1 0 0 k
L 7 0 0 1
2 . 2 u H
L 7 0 0 2
1 0 u H
C 7 0 0 5
0 . 0 1 u
R 7 0 3 8
1 k
Q 7 0 0 1
U N R 9 2 A 3 G 0 8 S 0
Q 7 0 0 2
2 S A 2 1 7 4 G R 8 S 0
R 7 0 4 0
4 7 k
R 7 0 3 9
X X
V A P _ D D _ O N
R 7 0 4 2
1 k
Q7003
UNR92A3G08S0
Q7004
2SA2174GR8S0
R 7 0 4 3
4 7 k
R 7 0 4 1
X X
R 7 0 4 4
X X
R 7 0 2 5
X X
R 7 0 2 1
1 0 0
R 7 0 2 8
1 0 0 k
R E G _ G N D
C L K
R E G _ G N D
P I T C H _ A D
D A T A
Y A W _ A D
C A M _ S O
C A M _ S I
C A M _ S C K
X C S _ S I O _ C A M
R 7 0 5 0
X X
R 7 0 5 1
X X
C L 7 0 1 4
C L 7 0 1 3
C L 7 0 0 7
C L 7 0 0 8
C L 7 0 0 9
C L 7 0 1 0
C L 7 0 1 1
C L 7 0 1 2
C L 7 0 1 7
A _ 2 . 8 V _ I C _ 7 0 0 1
D _ 2 . 8 V _ I C _ 7 0 0 1
R 7 0 2 9
0
P I T C H _ H A L L +
Y A W _ H A L L +
PITCH_AD_IC_7001
PIT
YAW_AD_IC_7001
Y
1 2
3
B
1 3
G
1 4
G
I
H
1 5
E
1 0
1 1
B
D
E
6
K
F
K
D
L
L
0 8
A
H
A
5
7
C
J
1 6
9
I
8
1
4
2
C
F
J
P I T C H / Y A W D R I V E
X X M A R K : N O M O U N T
P I T C H / Y A W D R I V E
B + S W I T C H
B + S W I T C H
B+ SWITCH
B+ SWITCH
X R S T _ I C _ 7 0 0 1
XRST_IC_7001
V C - 5 4 3 B O A R D ( 2 3 / 2 4 )
X R S T _ I C _ 7 0 0 1 _ C P U
VC-543 (23/24)
Summary of Contents for DSR-PD198P
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