SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD
Page 132
Version 0.7
10.8.6 STOP Condition Timing
At the end of received/transmitted, a STOP signal present on SDA pin by setting the STOP bit register, PEN
(MSPM2.1). At the end of receive/transmit, SCL goes low on the failing edge of ninth clock. Master will set SDA go low,
when set PEN bit. When SDA is sampled low, MSP rate generator is reloaded and start count down to 0. When MRG
overflow, SCL pin is pull high. After one T
MRG
period, SDA goes High. When SDA is sampled high while SCL is high, bit
P is set. PEN bit is clear after next one T
MRG
period, and MSPIRQ is set.
z
WCOL Status Flag
If user write to MSPBUF when a STOP condition is processing, then WCOL bit is set and the content of MSPBUF data
is un-changed. (the writer doesn’t occur)
SDA
SCL
T
MRG
T
MRG
Falling edge of ninth edge
P
P bit is set
T
MRG
Set PEN here
SDA goes low before the rising edge of SCL
to set up STOP signal
SCL goes high on next T
MRG
T
MRG
PEN is clear by hardware and
MSPIRQ bit is set
STOP condition sequence Timing Diagram
10.8.7 Clock Arbitration
Clock arbitration occurs when the master, during any receive, transmit or Repeat START, STOP condition that SCL pin
allowed to float high. When SCL pin is allowed float high, the master rate generator (MRG) suspended from counting
until the SCL pin is actually sampled high. When SCL is sampled high, the MRG is reloaded with the content of
MSPADDR[6:0], and start down counter. This ensure that SCL high time will always be at least one MRG overflow time
in the event that the clock is held low by an external device.
Clock Arbitration sequence Timing Diagram
