SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD
Page 122
Version 0.7
0 = Acknowledge was received from slave
1 = Acknowledge was not received from slave
Bit 5
ACKDT
: Acknowledge Data bit. (In master mode only)
In master receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
0 = Acknowledge
1 = Not Acknowledge
bit 4
ACKEN
: Acknowledge Sequence Enable bit (In MSP master mode only)
In master receive mode:
0 = Acknowledge sequence idle
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit AKDT data bit. Automatically
cleared by hardware.
bit 3
RCEN:
Receive Enable bit (In master mode only)
0 = Receive idle
1 = Enables Receive mode for MSP
bit 2
PEN:
Stop Condition Enable bit (In master mode only)
0 = Stop condition idle
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
bit 1
RSEN:
Repeated Start Condition Enabled bit (In master mode only)
0 = Repeated Start condition idle.
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
bit 0
SEN:
Start Condition Enabled bit (In master mode only)
0 = Start condition idle
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
10.5 MSP MSPBUF REGISTER
MSPBUF initial value = 0000 0000
093H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MSPBUF
MSPBUF7 MSPBUF6 MSPBUF5 MSPBUF4 MSPBUF3 MSPBUF2 MSPBUF1 MSPBUF0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After
reset
0 0 0 0 0 0 0 0
10.6 MSP MSPADR REGISTER
MSPADR initial value = 0000 0000
094H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MSPADR
MSPADR7 MSPADR6 MSPADR5 MSPADR4 MSPADR3 MSPADR2 MSPADR1 MSPADR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After
reset
0 0 0 0 0 0 0 0
Bit [7:1]
7-bit Address.
Bit 0
Tx/Rx mode control bit.
0=Tx mode.
1=Rx mode.
