SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD
Page 128
Version 0.7
10.8 Master mode
Master mode of MSP operation from a START signal and end by STOP signal.
The START (S) and STOP (P) bit are clear when reset or MSP function disabled.
In Master mode the SCL and SDA line are controlled by MSP hardware.
Following events will set MSP interrupt request (MSPIRQ), if MSPIEN set, interrupt occurs.
¾
START
condition
¾
STOP
condition
¾
Data byte transmitted or received
¾
Acknowledge
Transmit.
¾
Repeat
START.
10.8.1 Mater Mode Support
Master mode enable when MSPC and MSPENB bit set. Once the Master mode enabled, the user had following six
options.
¾
Send a START signal on SCL and SDA line.
¾
Send a Repeat START signal on SCL and SDA line.
¾
Write to MSPBUF register for Data or Address byte transmission
¾
Send a STOP signal on SCL and SDA line.
¾
Configuration MSP port for receive data
¾
Send an Acknowledge at the end of a received byte of data.
10.8.2 MSP Rate Generator
In MSP Mode, the MSP rate generator’s reload value is located in the lower 7 bit of MSPADDR register. When MRG is
loaded with the register, the MRG count down to 0 and stop until another reload has taken place. In MSP mater mode
MRG reload from MSPADDR automatically. If Clock Arbitration occur for instance (SCL pin keep low by Slave device),
the MRG will reload when SCL pin is detected High.
SCL clock rate =
Fcpu/(MSPADDR)*2
For example, if we want to set 400Khz in 4Mhz Fcpu, the MSPADDR have to set 0x05h.
MSPADDR=4Mhz/400Khz*2=5
MSP Rate Generator Block Diagram
