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SN8P275X Series

8-bit micro-controller build-in 12-bit ADC

SONiX TECHNOLOGY CO., LTD

Page 142

Version 0.7

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DIGITAL TO ANALOG CONVERTER

12.1 OVERVIEW

The D/A converter uses 7-bit structure to synthesize 128 steps' analog signal with current source output. After DAENB
bit is set to “1”, DAC circuit will turn to be enabled and the DAM register, from bit0 to bit6, will send digital signal to
ladder resistors in order to generate analog signal on DAO pin.

LADDER RESISTORS

DAM REGISTER

DAO OUTPUT

LADDER RESISTORS

DAM REGISTER

DAO OUTPUT

The DA converter Block Diagram

In order to get a proper linear output, a Loading Resistor R

L

is usually added between DAO and Ground. The example

shows the result of Vdd = 5V, R

L

=150ohm and Vdd = 3V, R

L

=150ohm.

DAO Circuit with R

L

DAC Output Voltage in Vdd=5V and 3V

Note:

1:The D/A converter is not designed for a precise DC voltage output and is suitable for a simple

audio application e.g. Tone or Melody generation.

2:For best linearity performance, the max. Loading Resistance R

L

is 150 ohm @5V, 100 ohm @3V

Vdd=3V

Vdd=5V

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Summary of Contents for SN8P2754

Page 1: ...d intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the...

Page 2: ...st issue VER 0 2 Nov 2008 1 Modify Package information VER 0 3 Nov 2008 1 Modify ICE MSP emulation VER 0 4 Feb 2008 1 Modify MSP Package information VER 0 5 Apr 2009 1 Modify SOP32 Package size VER 0...

Page 3: ...BLE DESCRIPTION 19 2 1 1 4 JUMP TABLE DESCRIPTION 21 2 1 1 5 CHECKSUM CALCULATION 23 2 1 2 CODE OPTION TABLE 24 2 1 3 DATA MEMORY RAM 25 2 1 4 SYSTEM REGISTER 26 2 1 4 1 SYSTEM REGISTER TABLE 26 2 1 4...

Page 4: ...48 3 6 2 Diode RC Reset Circuit 49 3 6 3 Zener Diode Reset Circuit 49 3 6 4 Voltage Bias Reset Circuit 50 3 6 5 External Reset IC 51 4 4 4 SYSTEM CLOCK 52 4 1 OVERVIEW 52 4 2 CLOCK BLOCK DIAGRAM 52 4...

Page 5: ...7 7 2 I O PULL UP REGISTER 79 7 3 I O PORT DATA REGISTER 80 7 4 I O OPEN DRAIN REGISTER 81 7 5 PORT 4 ADC SHARE PIN 82 8 8 8 TIMERS 84 8 1 WATCHDOG TIMER 84 8 2 TIMER 0 T0 86 8 2 1 OVERVIEW 86 8 2 2 T...

Page 6: ...OPERATION 114 9 3 SIOM MODE REGISTER 116 9 4 SIOB DATA BUFFER 117 9 5 SIOR REGISTER DESCRIPTION 118 1 1 10 0 0 MAIN SERIAL PORT MSP 119 10 1 OVERVIEW 119 10 2 MSP STATUS REGISTER 119 10 3 MSP MODE REG...

Page 7: ...12 3 D A CONVERTER OPERATION 143 1 1 13 3 3 INSTRUCTION TABLE 144 1 1 14 4 4 ELECTRICAL CHARACTERISTIC 145 14 1 ABSOLUTE MAXIMUM RATING 145 14 2 STANDARD ELECTRICAL CHARACTERISTIC 145 1 1 15 5 5 APPLI...

Page 8: ...ller build in 12 bit ADC SONiX TECHNOLOGY CO LTD Page 8 Version 0 7 16 6 LQFP 48 PIN 154 1 1 17 7 7 MARKING DEFINITION 155 17 1 INTRODUCTION 155 17 2 MARKING INDETIFICATION SYSTEM 155 17 3 MARKING EXA...

Page 9: ...Internal low clock RC type 16KHz 3V 32KHz 5V Internal high clock RC type 16MHz SIO function Operating modes Normal mode Both high and low clock active Powerful instructions Slow mode Low clock only O...

Page 10: ...8 SOP28 1 2 SYSTEM BLOCK DIAGRAM PC IR OTP ROM H OSC TIMING GENERATOR RAM SYSTEM REGISTER ALU ACC INTERRUPT CONTROL TIMER COUNTER PORT 0 PORT 2 PORT 1 PORT 4 PORT 5 FLAGS DAC ADC DAO AIN0 AIN7 SIO TX...

Page 11: ...4 2 AIN2 10 19 P5 1 SI P4 1 AIN1 11 18 P5 2 SO P4 0 AIN0 12 17 P5 3 TC1 PWM1 AVREFH 13 16 P5 4 TC0 PWM0 VDD 14 15 DAO SN8P2754K SN8P2754S SN8P2755P P DIP32 SN8P2755S SOP32 VSS 1 U 32 P5 0 SCK XOUT P3...

Page 12: ...18 31 P4 3 AIN3 SDA P1 1 19 30 P4 4 AIN4 SCL P1 0 20 29 P4 5 AIN5 P2 0 21 28 P4 6 AIN6 P2 1 22 27 P4 7 AIN7 P2 2 23 26 AVREFL P2 3 24 25 VSS SN8P2758X SN8P2758F LQFP48 P2 4 P5 0 SCK P5 1 SI P5 2 SO P...

Page 13: ...e as input mode Built in pull up resisters MSP serial clock input output pin Programmable open drain P1 1 SDA I O Port P1 1 bi direction pin and open drain pin Schmitt trigger structure as input mode...

Page 14: ...5 PIN CIRCUIT DIAGRAMS Port 1 0 P1 1 P5 2 structure Pull Up Pin Output Latch PnM PnUR Input Bus PnM Output Bus P1OC Open Drain Port 0 1 2 3 5 structure Pull Up Pin Output Latch PnM PnUR Input Bus PnM...

Page 15: ...SOR UNIT CPU 2 1 MEMORY MAP 2 1 1 PROGRAM MEMORY ROM 4K words ROM ROM 0000H Reset vector User reset vector Jump to user start address 0001H 0007H General purpose area 0008H Interrupt vector User inter...

Page 16: ...address ORG 10H START 0010H The head of user program User program ENDP End of program 2 1 1 2 INTERRUPT VECTOR 0008H A 1 word vector address area is used to execute interrupt request If any interrupt...

Page 17: ...SN8P275X Series 8 bit micro controller build in 12 bit ADC SONiX TECHNOLOGY CO LTD Page 17 Version 0 7 START The head of user program User program JMP START End of user program ENDP End of program...

Page 18: ...of user program User program JMP START End of user program MY_IRQ The head of interrupt service routine PUSH Save ACC and PFLAG register to buffers POP Load ACC and PFLAG register from buffers RETI En...

Page 19: ...okup table1 s low address MOVC To lookup data R 00H ACC 35H Increment the index address for next address INCMS Z Z 1 JMP F Z is not overflow INCMS Y Z is overflow Y Y 1 JMP F Y is not overflow INCMS X...

Page 20: ...DW 5105H DW 2012H The other example of loop up table is to add X Y or Z index register by accumulator Please be careful if carry happen Example Increase Y and Z register by B0ADD ADD instruction B0MO...

Page 21: ...arry after PCL ACC PCH adds one automatically If PCL borrow after PCL ACC PCH keeps value and not change Example Jump table ORG 0X0100 The jump table is from the head of the ROM boundary B0ADD PCL A P...

Page 22: ...ble routine begin from next ROM boundary 0x0100 Example JMP_A operation Before compiling program ROM address B0MOV A BUF0 BUF0 is from 0 to 4 JMP_A 5 The number of the jump table listing is five 0X00F...

Page 23: ...end address to end_addr2 CLR Y Set Y to 00H CLR Z Set Z to 00H MOVC B0BSET FC Clear C flag ADD DATA1 A Add A to Data1 MOV A R ADC DATA2 A Add R to Data2 JMP END_CHECK Check if the YZ address the end o...

Page 24: ...on cycle is oscillator clock Notice In Fosc 1 Noise Filter must be disabled Fhosc 2 Instruction cycle is 2 oscillator clocks Notice In Fosc 1 Noise Filter must be disabled Fhosc 4 Instruction cycle is...

Page 25: ...RAM Address RAM location 000h 000h 07Fh of Bank 0 To store general purpose data 128 bytes 07Fh General purpose area 080h 080h 0FFh of Bank 0 store system registers 128 bytes System register BANK 0 0FF...

Page 26: ...g register PFLAG ROM page and special flag register RBANK RAM Bank Select register DAM DAC s mode register ADM ADC s mode register ADB ADC s data buffer ADR ADC s resolution selects register SIOM SIO...

Page 27: ...YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0 R W Y 085H XBIT7 XBIT6 XBIT5 XBIT4 XBIT3 XBIT2 XBIT1 XBIT0 R W X 086H NT0 NPD C DC Z R W PFLAG 087H RBNKS0 R W RBANK 088H 089H 08AH 08BH 08CH 08DH 08EH 08FH...

Page 28: ...SIOB1 SIOB0 R W SIOB 0B7H 0B8H P02M P01M P00M R W P0M 0B9H 0BAH 0BBH 0BCH 0BDH 0BEH 0BFH P02G1 P02G0 P01G1 P01G0 P00G1 P00G0 R W PEDGE Address 0C0H 0DFH Addr Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R...

Page 29: ...TC1CKS ALOAD1 TC1OUT PWM1OUT R W TC1M 0DDH TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 TC1C2 TC1C1 TC1C0 R W TC1C 0DEH TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 TC1R0 W TC1R 0DFH GIE STKPB2 STKPB1 STKPB0 R W STKP...

Page 30: ...C2 S2PC1 S2PC0 R W STK2L 0FBH S2PC11 S2PC10 S2PC9 S2PC8 R W STK2H 0FCH S1PC7 S1PC6 S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 R W STK1L 0FDH S1PC12 S1PC11 S1PC10 S1PC9 S1PC8 R W STK1H 0FEH S0PC7 S0PC6 S0PC5...

Page 31: ...a immediate data into ACC MOV A 0FH Write ACC data from BUF data memory MOV A BUF The system doesn t store ACC and PFLAG value when interrupt executed ACC and PFLAG data must be saved to other data m...

Page 32: ...flag NT0 NPD Reset Status 0 0 Watch dog time out 0 1 Reserved 1 0 Reset by LVD 1 1 Reset by external Reset Pin Bit 2 C Carry flag 1 Addition with carry subtraction without borrowing rotation with shi...

Page 33: ...11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 After reset 0 0 0 0 0 0 0 0 0 0 0 0 PCH PCL ONE ADDRESS SKIPPING There are n...

Page 34: ...NCS BUF0 JMP C0STEP Jump to C0STEP if ACC is not zero C0STEP NOP INCMS instruction INCMS BUF0 JMP C0STEP Jump to C0STEP if BUF0 is not zero C0STEP NOP If the destination decreased by 1 which results u...

Page 35: ...A Jump to address 0328H PC 0328H MOV A 00H B0MOV PCL A Jump to address 0300H Example If PC 0323H PCH 03H PCL 23H PC 0323H B0ADD PCL A PCL PCL ACC the PCH cannot be changed JMP A0POINT If ACC 0 jump t...

Page 36: ...et location 20H for L register B0MOV A HL To read a data into ACC Example Clear general purpose data memory area of bank 0 using HL register CLR H H 0 bank 0 B0MOV L 07FH L 7FH the last address of the...

Page 37: ...ta in the RAM address 025H of bank0 B0MOV Y 00H To set RAM bank 0 for Y register B0MOV Z 25H To set location 25H for Z register B0MOV A YZ To read a data into ACC Example Uses the Y Z register as data...

Page 38: ...For store high byte data of look up table MOVC instruction executed the high byte data of specified ROM address will be stored in R register and the low byte data will be stored in ACC 082H Bit 7 Bit...

Page 39: ...out of ACC Example Move 0x12 RAM location data into ACC B0MOV A 12H To get a content of RAM location 0x12 of bank 0 and save in ACC Example Move ACC data into 0x12 RAM location B0MOV 12H A To get a co...

Page 40: ...instruction are executed The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer The STKnH and STKnL are the stack buffers to store program cou...

Page 41: ...terrupt service routine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 0DFH Bit 7 Bit 6 Bit...

Page 42: ...H STK1L 3 1 0 0 STK2H STK2L 4 0 1 1 STK3H STK3L 5 0 1 0 STK4H STK4L 6 0 0 1 STK5H STK5L 7 0 0 0 STK6H STK6L 8 1 1 1 STK7H STK7L 8 1 1 0 Stack Over error There are Stack Restore operations correspond t...

Page 43: ...og reset Watchdog timer overflow 0 1 Reserved 1 0 Power on reset and LVD reset Power voltage is lower than LVD detecting level 1 1 External reset External reset pin detect low level status Finishing a...

Page 44: ...program Under error condition system is in unknown situation and watchdog can t be clear by program before watchdog timer overflow Watchdog timer overflow occurs and the system is reset After watchdo...

Page 45: ...band V1 doesn t touch the below area and not effect the system operation But the V2 and V3 is under the below area and may induce the system error occurrence Let system under dead band includes some c...

Page 46: ...tem minimum operating voltage rises when the system executing rate upper even higher than system reset voltage The dead band definition is the system minimum operating voltage above the system reset v...

Page 47: ...dead band and the execution error the watchdog timer can t be clear by program The watchdog is continuously counting until overflow occurrence The overflow signal of watchdog timer triggers the syste...

Page 48: ...initialization All system registers is set as initial conditions and system is ready z Oscillator warm up Oscillator operation is successfully and supply to system clock z Program executing Power on...

Page 49: ...t circuit and Diode RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Electr...

Page 50: ...e right R1 R2 value to conform the application In the circuit diagram condition the MCU s reset pin level varies with VDD voltage variation and the differential voltage is 0 7V If the VDD drops and th...

Page 51: ...MCU VDD VSS VCC GND RST Reset IC VDD VSS RST Bypass Capacitor 0 1uF The external reset circuit also use external reset IC to enhance MCU reset performance This is a high cost and good effect solution...

Page 52: ...4 to be the instruction cycle Fcpu Normal Mode High Clock Fcpu Fhosc N N 1 128 Select N by Fcpu code option Slow Mode Low Clock Fcpu Flosc 4 SONIX provides a Noise Filter controlled by code option In...

Page 53: ...lator free run stop Internal low speed RC oscillator is still running Bit 2 CLKMD System high Low clock mode control bit 0 Normal dual mode System clock is high clock 1 Slow mode System clock is inter...

Page 54: ...y IHRC_16M or IHRC_RTC code options In IHRC_16M mode the system clock is from internal 16MHz RC type oscillator and XIN XOUT pins are general purpose I O pins In IHRC_RTC mode the system clock is from...

Page 55: ...normal speed ex 4MHz 32K option is for low speed ex 32768Hz MCU VCC GND C 20pF XIN XOUT VDD VSS C 20pF CRYSTAL Note Connect the Crystal Ceramic and C as near as possible to the XIN XOUT VSS pins of mi...

Page 56: ...Selecting external clock signal input to be system clock is by RC option of High_Clk code option The external clock signal is input from XIN pin XOUT pin is general purpose I O pin MCU VCC GND VSS VDD...

Page 57: ...0 00 25 00 30 00 35 00 40 00 45 00 2 1 2 5 3 3 1 3 3 3 5 4 4 5 5 5 5 6 6 5 7 VDD V Freq KHz ILRC The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD Flosc Inter...

Page 58: ...nstruction cycle Fcpu This way is useful in RC mode Example Fcpu instruction cycle of external oscillator B0BSET P0M 0 Set P0 0 to be output mode for outputting Fcpu toggle signal B0BSET P0 0 Output F...

Page 59: ...e Out External Reset Circuit Active System Mode Switching Diagram Operating mode description MODE NORMAL SLOW GREEN POWER DOWN SLEEP REMARK EHOSC Running By STPHX By STPHX Stop ILRC Running Running Ru...

Page 60: ...peed oscillator is still running B0BCLR FCLKMD To set CLKMD 0 Example Switch slow mode to normal mode The external high speed oscillator stops If external high clock stop and program want to switch ba...

Page 61: ...0H B0MOV T0M A To set T0 clock Fcpu 64 MOV A 74H B0MOV T0C A To set T0C initial value 74H To set T0 interval 10 ms B0BCLR FT0IEN To disable T0 interrupt service B0BCLR FT0IRQ To clear T0 interrupt req...

Page 62: ...5 3 2 WAKEUP TIME When the system is in power down mode sleep mode the high clock oscillator stops When waked up from power down mode MCU waits for 4096 external high speed oscillator clocks as the w...

Page 63: ...o wake the system up to normal mode The Port 0 and Port 1 have wakeup function Port 0 wakeup function always enables but the Port 1 is controlled by the P1W register 0C0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3...

Page 64: ...keup the chip while the system is switched from power down mode to high speed normal mode and interrupt request is latched until return to normal mode Once interrupt service is executed the GIE bit in...

Page 65: ...control bit 0 Disable INT0 interrupt function 1 Enable INT0 interrupt function Bit 1 P01IEN External P0 1 interrupt INT1 control bit 0 Disable INT1 interrupt function 1 Enable INT1 interrupt function...

Page 66: ...IRQ External P0 0 interrupt INT0 request flag 0 None INT0 interrupt request 1 INT0 interrupt request Bit 1 P01IRQ External P0 1 interrupt INT1 request flag 0 None INT1 interrupt request 1 INT1 interru...

Page 67: ...Set global interrupt control bit GIE B0BSET FGIE Enable GIE Note The GIE bit must enable during all interrupt operation 6 5 PUSH POP ROUTINE When any interrupt occurs system will jump to ORG 8 and exe...

Page 68: ...SN8P275X Series 8 bit micro controller build in 12 bit ADC SONiX TECHNOLOGY CO LTD Page 68 Version 0 7 RETI Exit interrupt service vector ENDP...

Page 69: ...configuration the trigger edge will be latched and the system executes interrupt service routine fist after wake up 0BFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDGE P02G1 P02G0 P01G1 P01G0...

Page 70: ...terrupt request setup B0BCLR FT0IEN Disable T0 interrupt service B0BCLR FT0ENB Disable T0 timer MOV A 20H B0MOV T0M A Set T0 clock Fcpu 64 MOV A 74H Set T0C initial value 74H B0MOV T0C A Set T0 interv...

Page 71: ...tuation Example TC0 interrupt request setup B0BCLR FTC0IEN Disable TC0 interrupt service B0BCLR FTC0ENB Disable TC0 timer MOV A 20H B0MOV TC0M A Set TC0 clock Fcpu 64 MOV A 74H Set TC0C initial value...

Page 72: ...tuation Example TC1 interrupt request setup B0BCLR FTC1IEN Disable TC1 interrupt service B0BCLR FTC1ENB Disable TC1 timer MOV A 20H B0MOV TC1M A Set TC1 clock Fcpu 64 MOV A 74H Set TC1C initial value...

Page 73: ...n t execute interrupt vector even when the SIOIEN is set to be 1 Users need to be cautious with the operation under multi interrupt situation Example SIO interrupt request setup B0BSET FSIOIEN Enable...

Page 74: ...tion under multi interrupt situation Example ADC interrupt request setup B0BCLR FADCIEN Disable ADC interrupt service MOV A 10110000B B0MOV ADM A Enable P4 0 ADC input and ADC function MOV A 00000000B...

Page 75: ...the events without enable the interrupt Once the event occurs the IRQ will be logic 1 The IRQ and its trigger event relationship is as the below table Interrupt Name Trigger Event Description P00IRQ...

Page 76: ...BTS1 FT0IEN Check T0IEN JMP INTTC0CHK Jump check to next interrupt B0BTS0 FT0IRQ Check T0IRQ JMP INTT0 Jump to T0 interrupt service routine INTTC0CHK Check TC0 interrupt request B0BTS1 FTC0IEN Check T...

Page 77: ...M P24M P23M P22M P21M P20M Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 0C3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P3M P32M P31M P30M Read Write R W R W R W After r...

Page 78: ...LOGY CO LTD Page 78 Version 0 7 Example I O mode selecting CLR P0M Set all ports to be input mode CLR P4M CLR P5M MOV A 0FFH Set all ports to be output mode B0MOV P0M A B0MOV P4M A B0MOV P5M A B0BCLR...

Page 79: ...1 Bit 0 P2UR P27R P26R P25R P24R P23R P22R P21R P20R Read Write W W W W W W W W After reset 0 0 0 0 0 0 0 0 0E3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P3UR P32R P31R P30R Read Write W W W Af...

Page 80: ...it 3 Bit 2 Bit 1 Bit 0 P3 P33 P32 P31 P30 Read Write R W R W R W R W After reset 0 0 0 0 0D4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P4 P47 P46 P45 P44 P43 P42 P41 P40 Read Write R W R W R W...

Page 81: ...P10OC Read Write W W W After reset 0 0 0 Bit 2 P52OC P5 2 open drain control bit 0 Disable open drain mode 1 Enable open drain mode Bit 1 P11OC P1 1 open drain control bit 0 Disable open drain mode 1...

Page 82: ...P4CON5 P4CON4 P4CON3 P4CON2 P4CON1 P4CON0 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 4 0 P4CON 7 0 P4 n configuration control bits 0 P4 n can be an analog input ADC inp...

Page 83: ...LR P4CON 1 Enable P4 1 digital function Enable P4 1 input mode B0BCLR P4M 1 Set P4 1 as input mode Example Set P4 1 to be general purpose output P4CON 1 must be set as 0 Check GCHS and CHS 2 0 status...

Page 84: ...g Overflow Time 3V 16KHz 512ms 5V 32KHz 256ms Note 1 If watchdog is Always_On mode it keeps running event under power down mode or green mode 2 For S8KD ICE simulation clear watchdog timer using RST_W...

Page 85: ...ervice routine That can improve main routine fail z Clearing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Example An...

Page 86: ...owing 8 bit programmable up counting timer Generates interrupts at specific time intervals based on the selected clock frequency RTC timer Generates interrupts at real time intervals based on the sele...

Page 87: ...68 cyrstal Bit 2 TC0X8 TC0 internal clock source control bit 0 TC0 internal clock source is Fcpu TC0RATE is from Fcpu 2 Fcpu 256 1 TC0 internal clock source is Fosc TC0RATE is from Fosc 1 Fosc 128 Bit...

Page 88: ...ect T0RATE 010 Fcpu 64 T0C initial value 256 T0 interrupt interval time input clock 256 10ms 4MHz 4 64 256 10 2 4 106 4 64 100 64H The basic timer table interval time of T0 High speed mode Fcpu 4MHz 4...

Page 89: ...pt function is disabled B0BCLR FT0IRQ T0 interrupt request flag is cleared Set T0 timer rate MOV A 0xxx0000b The T0 rate control bits exist in bit4 bit6 of T0M The value is from x000xxxxb x111xxxxb B0...

Page 90: ...time out signal to trigger TC0 interrupt to request interrupt service TC0 overflow time is 0xFF to 0X00 normally Under PWM mode TC0 overflow is still 256 counts The main purposes of the TC0 timer is a...

Page 91: ...gnal output control bit Only valid when PWM0OUT 0 0 Disable P5 4 is I O function 1 Enable P5 4 is output TC0OUT signal Bit 2 ALOAD0 Auto reload control bit Only valid when PWM0OUT 0 0 Disable TC0 auto...

Page 92: ...64 TC0C initial value 256 TC0 interrupt interval time input clock 256 10ms 4MHz 4 64 256 10 2 4 106 4 64 100 64H The basic timer table interval time of TC0 High speed mode Fcpu 4MHz 4 Low speed mode F...

Page 93: ...types TC0 timer TC0 event counter TC0 Fcpu clock source PWM mode and no PWM mode These parameters decide TC0 overflow time and valid value as follow table TC0CKS PWM0 ALOAD0 TC0OUT N TC0R valid value...

Page 94: ...frequency waveform is as following 1 2 3 4 1 2 3 4 TC1 Overflow Clock TC1OUT Buzzer Output Clock Example Setup TC0OUT output from TC0 to TC0OUT P5 4 The external high speed clock is 4MHz The TC0OUT fr...

Page 95: ...r clock source Select TC0 internal external clock source B0BCLR FTC0CKS Select TC0 internal clock source or B0BSET FTC0CKS Select TC0 external clock source Set TC0 timer auto load mode B0BCLR FALOAD0...

Page 96: ...d from 0 to 1 B0BSET FTC0IEN Enable TC0 interrupt function and system jumps to interrupt vector ORG 8 at next cycle If TC0C changing in system operating duration is necessary to disable TC0 interrupt...

Page 97: ...time out signal to trigger TC1 interrupt to request interrupt service TC1 overflow time is 0xFF to 0X00 normally Under PWM mode TC1 overflow is still 256 counts The main purposes of the TC1 timer is a...

Page 98: ...gnal output control bit Only valid when PWM1OUT 0 0 Disable P5 3 is I O function 1 Enable P5 3 is output TC1OUT signal Bit 2 ALOAD1 Auto reload control bit Only valid when PWM1OUT 0 0 Disable TC1 auto...

Page 99: ...nitial value 256 TC1 interrupt interval time input clock 256 10ms 4MHz 4 64 256 10 2 4 106 4 64 100 64H The basic timer table interval time of TC1 High speed mode Fcpu 4MHz 4 Low speed mode Fcpu 32768...

Page 100: ...e types TC1 timer TC1 event counter TC1 Fcpu clock source PWM mode and no PWM mode These parameters decide TC1 overflow time and valid value as follow table TC1CKS PWM1 ALOAD1 TC1OUT N TC1R valid valu...

Page 101: ...frequency waveform is as following 1 2 3 4 1 2 3 4 TC1 Overflow Clock TC1OUT Buzzer Output Clock Example Setup TC1OUT output from TC1 to TC1OUT P5 3 The external high speed clock is 4MHz The TC1OUT fr...

Page 102: ...r clock source Select TC1 internal external clock source B0BCLR FTC1CKS Select TC1 internal clock source or B0BSET FTC1CKS Select TC1 external clock source Set TC1 timer auto load mode B0BCLR FALOAD1...

Page 103: ...ed from 0 to 1 B0BSET FTC1IEN Enable TC1 interrupt function and system jumps to interrupt vector ORG 8 at next cycle If TC1C changing in system operating duration is necessary to disable TC1 interrupt...

Page 104: ...h ratio duty of the PWM0 output is TC0R 256 64 32 16 Note TC0C and TC0R can be 0xFF in pure PWM output If PWM function is operating with TC0 interrupt TC0C and TC0R can t be set as 0xFF and the availa...

Page 105: ...TC0IRQ AND PWM DUTY In PWM mode the frequency of TC0IRQ is depended on PWM duty range From following diagram the TC0IRQ frequency is related with PWM duty TC0C Value PWM0 Output Duty Range 0 255 PWM0...

Page 106: ...01100000B B0MOV TC0M A Set the TC0 rate to Fcpu 4 MOV A 30 Set the PWM duty to 30 256 B0MOV TC0C A B0MOV TC0R A B0BCLR FTC0OUT Set duty range as 0 256 255 256 B0BCLR FALOAD0 B0BSET FPWM0OUT Enable PW...

Page 107: ...l change immediately If TC0R is fixed all the time the PWM waveform is also the same TC0C overflow and TC0IRQ set TC0C TC0R 0xFF TC0C Value 0x00 PWM0 Output 1 2 3 4 5 6 7 Period Above diagram is shown...

Page 108: ...ext cycle PWM outputs correct duty In period 4 the new TC0R value is smaller than the old TC0R value If setting new TC0R is before PWM output low system is getting TC0C TC0R result and making PWM outp...

Page 109: ...h ratio duty of the PWM1 output is TC1R 256 64 32 16 Note TC1C and TC1R can be 0xFF in pure PWM output If PWM function is operating with TC1 interrupt TC1C and TC1R can t be set as 0xFF and the availa...

Page 110: ...TC1IRQ AND PWM DUTY In PWM mode the frequency of TC1IRQ is depended on PWM duty range From following diagram the TC1IRQ frequency is related with PWM duty TC1C Value PWM1 Output Duty Range 0 255 PWM1...

Page 111: ...01100000B B0MOV TC1M A Set the TC1 rate to Fcpu 4 MOV A 30 Set the PWM duty to 30 256 B0MOV TC1C A B0MOV TC1R A B0BCLR FTC1OUT Set duty range as 0 256 255 256 B0BCLR FALOAD1 B0BSET FPWM1OUT Enable PW...

Page 112: ...l change immediately If TC1R is fixed all the time the PWM waveform is also the same TC1C overflow and TC1IRQ set TC1C TC1R 0xFF TC1C Value 0x00 PWM1 Output 1 2 3 4 5 6 7 Period Above diagram is shown...

Page 113: ...ext cycle PWM outputs correct duty In period 4 the new TC1R value is smaller than the old TC1R value If setting new TC1R is before PWM output low system is getting TC1C TC1R result and making PWM outp...

Page 114: ...ogrammable bit rates Only in master mode z End of Transfer interrupt 9 2 SIO OPERATION The SIOM register can control SIO operating function such as transmit receive clock rate data transfer direction...

Page 115: ...fixed already and the SCK first edge is to receive and transmit data The SIO data transfer timing as following figure M L S B C P O L C P H A Diagrams Description 0 0 1 SCK idle status Low The transfe...

Page 116: ...mode Enable SENB select CPOL and CPHA bits These bits control SIO pins mode 9 3 SIOM MODE REGISTER SIOM initial value 0000 0000 0B4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIOM SENB START SR...

Page 117: ...e and open drain structure controlled by P1OC register 9 4 SIOB DATA BUFFER SIOB initial value 0000 0000 0B6H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SIOB SIOB7 SIOB6 SIOB5 SIOB4 SIOB3 SIOB2 S...

Page 118: ...0 0 0 0 The SIOR is designed for the SIO counter to reload the counted value when end of counting It is like a post scaler of SIO clock source and let SIO has more flexible to setting SCK range Users...

Page 119: ...function reference Ch15 1 1 10 2 MSP STATUS REGISTER MSPSTAT initial value X000 00X0 090H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSPSTAT CKE D_A P S RED_WRT BF Read Write R W R R R R R After...

Page 120: ...te R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Bit 7 WCOL Write Collision Detect bit Master Mode 0 No collision 1 A write to the SSPBUF register was attempted while the MSP conditions were n...

Page 121: ...ing Power down mode for indication the wake up source from MSP or not Bit 0 MSPC MSP mode Control register 0 MSP operated on Slave mode 7 bit address 1 MSP operated on Master mode Note1 If MSP want to...

Page 122: ...Initiate Stop condition on SDA and SCL pins Automatically cleared by hardware bit 1 RSEN Repeated Start Condition Enabled bit In master mode only 0 Repeated Start condition idle 1 Initiate Repeated St...

Page 123: ...automatically when reading MSPBUF register MSPOV bit must be clear through by Sofrware 10 7 1 Addressing When MSP Slave function has been enabled it will wait a START signal occur Following the START...

Page 124: ...PBUF After reply an ACK_ signal MSP will receive data every 8 clock The CKP function enable or disable Default is controlled by SLRXCKP bit and data latch edge Rising edge Default or Falling edge is c...

Page 125: ...et After load MSPBUF set CKP bit MSPBUF data will shift out on the falling edge on SCL signal This will ensure the SDA signal is valid on the SCL high duty An MSP interrupt is generated on every byte...

Page 126: ...ll 0 of 7 bytes address The general call address function is control by GCEN bit Set this bit will enable general call address and clear it will disable When GECN 1 following a START signal 8 bit will...

Page 127: ...l register BF MSPIRQ MSPOV and MSPBUF will be the same status data before power down If address not matches a NOT acknowledge is still sent on the ninth clock of SCL but MCU will be NOT wake up and st...

Page 128: ...a START signal on SCL and SDA line Send a Repeat START signal on SCL and SDA line Write to MSPBUF register for Data or Address byte transmission Send a STOP signal on SCL and SDA line Configuration MS...

Page 129: ...ounter When SDA and SCL are both sampled high and MRG overflow SDA pin is drive low When SCL sampled high and SDA transmitted from High to Low is the START signal and will set S bit MSPSTAT 3 MRG relo...

Page 130: ...wn counter SDA and SCL must keep high in one TMRG period In the next TMRG period SDA will be brought low when SCL is sampled high then RSEN will clear automatically by hardware and MRG will not reload...

Page 131: ...r overflow MSP rate generator start a TMRG period down counter when SCL is sampled high After this period SCL is pulled low and ACKEN bit is clear automatically by hardware When next MRG overflow agai...

Page 132: ...hen WCOL bit is set and the content of MSPBUF data is un changed the writer doesn t occur SDA SCL TMRG TMRG Falling edge of ninth edge P P bit is set TMRG Set PEN here SDA goes low before the rising e...

Page 133: ...y accept by slave device The status of the ACK bit is load into ACKSTAT status bit Then MSPIRQ bit is set the BF bit is clear and the MRG is hold off until another write to the MSPBUF occurs holding S...

Page 134: ...MSP is now in IDLE mode and awaiting the next operation command When the MSPBUF data is read by Software the BF flag is cleat automatically By setting ACKEN bit user can send an acknowledge bit at th...

Page 135: ...DATA BUS 8 12 AIN0 P4 0 AIN0 P4 0 AIN5 P4 5 AIN5 P4 5 AIN2 P4 2 AIN2 P4 2 AIN3 P4 3 AIN3 P4 3 AIN4 P4 4 AIN4 P4 4 AIN1 P4 1 AIN1 P4 1 AIN6 P4 6 AIN6 P4 6 AIN7 P4 7 AIN7 P4 7 Note For 8 bit resolution...

Page 136: ...1 Enable Bit 6 ADS ADC start bit 0 Stop 1 Starting Bit 5 EOC ADC status bit 0 Progressing 1 End of converting and reset ADS bit Bit 4 GCHS Global channel select bit 0 Disable AIN channel 1 Enable AIN...

Page 137: ...R W R W R R R R After reset 0 0 0 0 Bit 7 6 4 ADCKS 2 0 ADC s clock source select bit ADCKS2 ADCKS1 ADCKS0 ADC Clock Source 0 0 0 Fcpu 16 0 0 1 Fcpu 8 0 1 0 Fcpu 1 0 1 1 Fcpu 2 1 0 0 Fcpu 64 1 0 1 Fc...

Page 138: ...oltage v s ADB s output data AIN n ADB1 1 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 ADB3 ADB2 ADB1 ADB0 0 4096 VREFH 0 0 0 0 0 0 0 0 0 0 0 0 1 4096 VREFH 0 0 0 0 0 0 0 0 0 0 0 1 4094 4096 VREFH 1 1 1 1 1 1...

Page 139: ...W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 4 0 P4CON 7 0 P4 n configuration control bits 0 P4 n can be an analog input ADC input or digital I O pins 1 P4 n is pure analog input can t be a digital I...

Page 140: ...4 0 pull up resistor B0BCLR FP40M Set P4 0 as input pin MOV A 01h B0MOV P4CON A Set P4 0 as pure analog input MOV A 60H B0MOV ADR A To set 12 bit ADC and ADC clock Fosc MOV A 90H B0MOV ADM A To enable...

Page 141: ...Signal Input 47uF 0 1uF ADC reference high voltage is from VDD pin The VERFH should be from MCU s VDD pin Don t connect from main power MCU VCC GND VREFH AINn P4 n VDD VSS 0 1uF Analog Signal Input 0...

Page 142: ...erate analog signal on DAO pin LADDER RESISTORS DAM REGISTER DAO OUTPUT LADDER RESISTORS DAM REGISTER DAO OUTPUT The DA converter Block Diagram In order to get a proper linear output a Loading Resisto...

Page 143: ...t 6 0 DAB 6 0 Digital input data 12 3 D A CONVERTER OPERATION When the DAENB 0 the DAO pin is output floating status After setting DAENB to 1 the DAO output value is controlled by DAB bits Example Out...

Page 144: ...I A A and I 1 G OR A M A A or M 1 I OR M A M A or M 1 N C OR A I A A or I 1 XOR A M A A xor M 1 XOR M A M A xor M 1 N XOR A I A A xor I 1 SWAP M A b3 b0 b7 b4 M b7 b4 b3 b0 1 P SWAPM M M b3 b0 b7 b4 M...

Page 145: ...Vin Vdd 2 uA I O output source current IoH Vop Vdd 0 5V 8 12 mA sink current IoL Vop Vss 0 5V 8 15 mA INTn trigger pulse width Tint0 INT0 INT2 interrupt request pulse width 2 fcpu Cycle AVREFH input v...

Page 146: ...Code NMC VDD 5 0V AVREFH 3 2V FADSMP 7 8K 8 10 12 Bits These parameters are for design reference not tested 1 1 15 5 5APPLICATION NOTICE 15 1 Development Tool Version 15 1 1 ICE In circuit emulation...

Page 147: ...r It s convenient to connect Full Speed USB 1 1 port with PC and then update the writer connect programming chip or download programming code 15 1 3 IDE Integrated Development Environment SONiX 8 bit...

Page 148: ...LSB PDB 20 19 DIP10 10 39 DIP39 DIP11 11 38 DIP38 JP1 for MP transition board DIP12 12 37 DIP38 JP2 for Writer V3 0 transition board DIP13 13 36 DIP36 DIP14 14 35 DIP35 DIP15 15 34 DIP34 DIP16 16 33 D...

Page 149: ...riter V3 0 OTP IC JP3 Pin Assignment Number Pin Number Pin Number Pin Number Pin 1 VDD 3 14 24 VDD 4 26 VDD 8 16 36 37 VDD 2 GND 7 21 VSS 1 16 VSS 5 25 VSS 3 CLK 20 P5 0 32 P5 0 47 P5 0 4 CE 5 PGM 6 P...

Page 150: ...SONiX TECHNOLOGY CO LTD Page 150 Version 0 7 1 1 16 6 6PACKAGE INFORMATION 16 1 SK DIP28 PIN Symbols MIN NOR MAX A 0 210 A1 0 015 A2 0 114 0 130 0 135 D 1 390 1 390 1 400 E 0 310BSC E1 0 283 0 288 0 2...

Page 151: ...bit micro controller build in 12 bit ADC SONiX TECHNOLOGY CO LTD Page 151 Version 0 7 16 2 SOP28 PIN Symbols MIN MAX A 0 093 0 104 A1 0 004 0 012 D 0 697 0 713 E 0 291 0 299 H 0 394 0 419 L 0 016 0 0...

Page 152: ...SN8P275X Series 8 bit micro controller build in 12 bit ADC SONiX TECHNOLOGY CO LTD Page 152 Version 0 7 16 3 P DIP 32 PIN 16 4 SOP 32 PIN...

Page 153: ...0 102 0 110 2 413 2 591 2 794 A1 0 008 0 012 0 016 0 203 0 305 0 406 A2 0 089 0 094 0 099 2 261 2 388 2 515 b 0 008 0 010 0 030 0 203 0 254 0 762 C 0 008 0 203 D 0 620 0 625 0 630 15 748 15 875 16 002...

Page 154: ...build in 12 bit ADC SONiX TECHNOLOGY CO LTD Page 154 Version 0 7 16 6 LQFP 48 PIN MIN NOR MAX SYMBOLS mm A 1 6 A1 0 05 0 15 A2 1 35 1 45 c1 0 09 0 16 D 9 00 BSC D1 7 00 BSC E 9 00 BSC E1 7 00 BSC e 0...

Page 155: ...line This note listed the production definition of all 8 bit MCU for order or obtain information This definition is only for Blank OTP MCU 17 2 MARKING INDETIFICATION SYSTEM SN8 X PART No X X X Title...

Page 156: ...3 MARKING EXAMPLE Name ROM Type Device Package Temperature Material SN8P2758XB OTP 2758 SSOP 0 70 PB Free Package 17 4 DATECODE SYSTEM X X X X XXXXX Year Month 1 January 2 February 9 September A Octo...

Page 157: ...ury or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affi...

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