SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD
Page 117
Version 0.7
Because SIO function is shared with Port5 for P5.0 as SCK, P5.1 as SI and P5.2 as SO. The following table shows the
Port5[2:0] I/O mode behavior and setting when SIO function enable and disable.
SENB=1 (SIO Function Enable)
(SCKMD=1)
SIO source = External clock
P5.0 will change to Input mode automatically, no matter what P5M
setting.
P5.0/SCK
(SCKMD=0)
SIO source = Internal clock
P5.0 will change to Output mode automatically, no matter what
P5M setting.
P5.1/SI
P5.1 must be set as Input mode in P5M ,or the SIO function will be abnormal
P5.2/SO
SIO = Transmitter/Receiver
P5.2 will change to Output mode automatically, no matter what
P5M setting.
SENB=0 (SIO Function Disable)
P5.0/P5.1/P5.2 Port5[2:0] I/O mode are fully controlled by P5M when SIO function Disable
Note: 1. If SCKMD=1 for external clock, the SIO is in SLAVE mode. If SCKMD=0 for internal clock,
the SIO is in MASTER mode.
2. Don’t set SENB and START bits in the same time. That makes the SIO function error.
3. SIO pin can be push-pull structure and open-drain structure controlled by P1OC register.
9.4 SIOB DATA BUFFER
SIOB initial value = 0000 0000
0B6H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SIOB
SIOB7 SIOB6 SIOB5 SIOB4 SIOB3 SIOB2 SIOB1 SIOB0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W
After
reset
0 0 0 0 0 0 0 0
SIOB is the SIO data buffer register. It stores serial I/O transmit and receive data. The system is single-buffered in the
transmit direction and double-buffered in the receive direction. This means that bytes to be transmitted cannot be
written to the SIOB Data Register before the entire shift cycle is completed. When receiving data, however, a received
byte must be read from the SIOB Data Register before the next byte has been completely shifted in. Otherwise, the
first byte is lost. Following figure shows a typical SIO transfer between two micro-controllers. Master MCU sends SCK
for initial the data transfer. Both master and slave MCU must work in the same clock edge direction, and then both
controllers would send and receive data at the same time.
Shift Register
(SIOB)
2nd Receive Buffer
(Address = SIOB)
Int
ernal B
u
s
Read SIOB
Write SIOB
SIO Master
(SCKMD = 0)
SO
SI
SCK
Shift Register
(SIOB)
2nd Receive Buffer
(Address = SIOB)
Int
ernal B
u
s
Read SIOB
Write SIOB
SIO Slave
(SCKMD = 1)
SI
SO
SCK
SIO Data Transfer Diagram
