SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD
Page 115
Version 0.7
The SIO supports 8-mode format controlled by MLSB, CPOL and CPHA bits. The edge direction is “Data Transfer
Edge”. When setting rising edge, that means to receive and transmit one bit data at SCK rising edge, and data
transition is at SCK falling edge. When setting falling edge, that means to receive and transmit one bit data at SCK
falling edge, and data transition is at SCK rising edge.
“CPHA” is the clock phase bit controls the phase of the clock on which data is sampled. When CPHA=1, the SCK first
edge is for data transition, and receive and transmit data is at SCK 2
nd
edge. When CPHA=0, the 1
st
bit is fixed already,
and the SCK first edge is to receive and transmit data. The SIO data transfer timing as following figure:
M
L
S
B
C
P
O
L
C
P
H
A
Diagrams
Description
0 0 1
SCK idle status = Low.
The transfer first bit = MSB.
SCK data transfer edge = Falling
edge.
0 1 1
SCK idle status = High.
The transfer first bit = MSB.
SCK data transfer edge = Rising
edge.
0 0 0
SCK idle status = Low.
The transfer first bit = MSB.
SCK data transfer edge = Rising
edge.
0 1 0
SCK idle status = High.
The transfer first bit = MSB.
SCK data transfer edge = Falling
edge.
1 0 1
SCK idle status = Low.
The transfer first bit = LSB.
SCK data transfer edge = Falling
edge.
1 1 1
SCK idle status = High.
The transfer first bit = LSB.
SCK data transfer edge = Rising
edge.
1 0 0
SCK idle status = Low.
The transfer first bit = LSB.
SCK data transfer edge = Rising
edge.
1 1 0
SCK idle status = High.
The transfer first bit = LSB.
SCK data transfer edge = Falling
edge.
SIO Data Transfer Timing
