Si4010-C2
52
Rev. 1.0
17.1. Register Description
SFR Address = 0x9B
SFR Definition 17.1. FC_CTRL
Bit
7
6
5
4
3
2
1
0
Name
FC_DONE FC_BUSY FC_DIV_
SEL
Reserved
FC_MODE[2:0]
Type
R/W
R/W
R/W
R
R/W
Reset
0
0
0
0
0
Bit
Name
Function
7
FC_DONE
Frequency Counter Done.
Counting done, interrupt generation level signal. Must be cleared by software ISR. It
is also cleared if 1 is written to fc_busy, which denotes the start of the next count. Any
value can be written here, so one can invoke interrupt just writing 1 here.
0: Frequency counter is counting
1: Frequency counter done counting, must be cleared by software ISR
6
FC_BUSY
Frequency Counter Busy.
Frequency counter is busy counting. Falling edge of the fc_busy signal sets the
FC_DONE=1. Writing 1 to this bit triggers a new FC counting cycle. FC is restartable,
so any Wr 1 to this bit restarts the FC and discards what the FC was currently doing.
0: Frequency counter is not busy, falling edge sets FC_DONE=1
1: Writing 1 restarts the Frequency Counter
5
FC_DIV_
SEL
Frequency Counter Divider Select.
Selection control of source of clock. It chooses between LC and DIVIDER. If the fre-
quency counter is not enabled, FC_MODE=0, then both signals mentioned above are
in their inactive states.
0: LCOSC
1: DIVIDER
4:3
Reserved
Read as 0x0. Write has no effect.
2:0
FC_MODE
[2:0]
Frequency Counter Mode Control Register.
000: Frequency counter disabled
001: Interval: clk_ref .. reference clock from GPIO
010: Interval: clk_osc .. undivided output of Low Power Osc (24 MHz)
011: Interval: clk_sys .. system clock, divided output of Low Power Osc
100: Interval: clk_xo .. XO oscillator
101: Reserved
110: Interval: Sleep Timer output
111: Reserved
