Rev. 1.0
125
Si4010-C2
5
CLKOUT_
SYM
CLKOUT Symmetry.
If this bit set to 1 then the output clock duty cycle is very close to 1:1 irrespective of
the division factor. However, the generated clock waveform is a combination of
outputs of two flops and therefore might jitter more. If this bit is 0 then for odd division
factor there is a single 24 MHz period difference in between halves of the generation
output clock.
This bit must be set before customer clock is enabled to the port output by setting
PORT_SET.PORT_CLKEN=1.
4:0
CLKOUT_
DIV[4:0]
CLKOUT Division Factor.
Division factor of the 24 MHz oscillator clock for generation of the output customer
clock. The enable of the clock is controlled by the PORT_CLKEN and
PORT_CLKOUT bits in PORT_SET register. The division factors 0 and 1 pass the
24 MHz internal cheap oscillator output as output clocks. Value bigger than 1 is the
actual division factor of the 24 MHz.
If CLKOUT_SYM=0 (recommended), the generated clock is an output of a flop. For
odd division ratios the first part of the period in logic 0 is one 24 MHz clock cycle
shorter than the second high half part of the period of generated clock, assuming
CLKOUT_INV=0.
If the clock is disabled by PORT_CLKEN=0 the current period in progress will be
finished. To monitor when the output gets idle monitor the CLKOUT_CLR bit of this
register.
The CLKOUT_DIV bit can be changed any time. The new setting will take effect only
after the current period finishes. For the new setting to take effect immediately see
CLKOUT_CLR.
Bit
Name
Function
