Silicon Laboratories Si4010-C2, Manual

Page: 85 / 157

Rev. 1.0 85
Si4010-C2
25. On-Chip Registers
There are two register regions on chip:

Special Function Registers region

XREG region
25.1. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the Si4010-C2's resources and peripherals.
The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as imple-
menting additional SFRs used to configure and access the sub-systems unique to the Si4010-C2. This
allows the addition of new functionality while retaining compatibility with the MCS-51™ instruction set.
Table 25.2
lists the SFRs implemented in the Si4010-C2 device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, P1, ACC, IE, etc.) are bit-address-
able as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the
SFR space are reserved for future use. Accessing these areas will have an indeterminate effect and
should be avoided. Refer to the corresponding pages of the data sheet, as indicated in Table 25.2, for a
detailed description of each register.
Table 25.1. Special Function Register (SFR) Memory Map
0X80 0x90 0xA0 0xB0 0xC0 0xD0 0xE0 0xF0
0*
P0* P1* P2* PSW* ACC* B*
1
SP GPR_CTRL
2
DPL GPR_DATA
3
DPH
4
GFM_DATA P0CON LC_FSK
5
GFM_CONST P1CON PORT_CTRL
6
SBOX_DATA PORT_SET EIE1 EIP1
7
PCON PORT_INTCFG
8*
IE* IP* TMR2CTRL*
9
RBIT_DATA ODS_CTRL TMR3CTRL TMR_CLKSEL
A
ODS_TIMING TMR3RL TMR2RL PROT0_CTRL
B
FC_CTRL ODS_DATA TMR3RH TMR2RH
C
RTC_CTRL ODS_RATEL TMR3L TMR2L
D
FC_INTERVAL ODS_RATEH TMR3H TMR2H BOOT_FLAGS
E
ODS_WARM1 SYSGEN PA_LVL SYS_SET
F
CLKOUT_SET ODS_WARMS2 INT_FLAGS
*Notes:
Bit addressable registers.