Si4010-C2
130
Rev. 1.0
SFR Address = 0x9C
SFR Definition 33.1. RTC_CTRL
Bit
7
6
5
4
3
2
1
0
Name
RTC_INT RTC_ENA RTC_CLR Reserved
Reserved
RTC_DIV[2:0]
Type
R/W
R/W
W
R
R
R/W
Reset
0
0
0
0
0
0
0
0
Bit
Name
Function
7
RTC_INT
Real Time Clock Interrupt Flag.
Set after the time interval set by RTC_DIV field elapses. Software must clear the flag.
Hardware will not clear the flag
6
RTC_ENA
Real Time Clock Enable.
If set to 1 then the RTC_TICK and bottom part of the pulse generator starts running
where it left off. If RTC_DIV >=3 then top half also starts.
0: RTC disabled
1: RTC enabled.
5
RTC_CLR
Real Time Clock Clear.
Writing 1 will clear the pulse generator but will leave the RTC_TICK generator intact.
See the RTC_TICKCLR in the SYSGEN register for clearing the RTC_TICK counter.
0: Normal operation
1: RTC cleared
4:3
Reserved
Read as 0x00. Write has no effect.
2:0
RTC_DIV
[2:0]
Real Time Clock Divider.
Select the divider of the RTC_TICK to determine the interval for the RTC interrupt
generation.
000: No interrupt generation
001: 100 µs .. it is a 19/19/19/18 divider
010: 200 µs .. it is a 38/37 divider
011: 400 µs
100: 800 µs
101: 1 ms
110: 2 ms
111: 5 ms
