Silicon Laboratories Si4010-C2 Manual Download Page 45 | Manualshive

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Rev. 1.0

45

Si4010-C2

SFR Address = 0xAF

SFR Definition 13.7. ODS_WARM2

Bit

7

6

5

4

3

2

1

0

Name

Reserved

ODS_WARM_LC[3:0]

Type

R

R/W

Reset

0

0

0

0

0

0

0

0

Bit

Name

Function

7:4

Reserved

Read as 0x0. Write has no effect.

3:0

ODS_

WARM_

LC[3:0]

Sets Warm-Up Time for the LCOSC.

Sets the "warm up" interval for the LC oscillator, where it is biased up prior to



transmission or on the transition from OOK zero bit to OOK one bit. Set this value in a
way that the warm-up interval of the LCOSC should be 125 µs for a given ODS clock
rate.
Interval is in 64 x clk_ods cycles resolution
Interval = 64 x ods_warm_lc x (ods1)/24 MHz
Using the Si4010 calculator spreadsheet in order to determine the correct value of
this parameter is

strongly recommended

.

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Summary of Contents for Si4010-C2

Page 1: ...ntenna impedance changes due to the remote being held in a user hand The devices supports FSK and OOK modulations and includes automatic output power shaping to reduce spectral spreading and ease regulatory compliance The output frequency can be adjusted via software over the entire 27 to 960 MHz range The output data rate is software adjustable up to a maximum rate of 100 kbps Crystal less operat...

Page 2: ... Functional Block Diagram Si4010 NVM 8 Kbyte EEPROM 128 bit VDD GND PA RAM ROM PUSH BUTTONS CR2032 COIN CELL 1 8 3 6 V DIVIDER I O INTERFACE GPIO 4 8 INTEGRATED 8051 MCU LDO REGULATOR TXM TXP LOOP ANTENNA FSK OOK LED VDD ...

Page 3: ...Land Pattern 10 Pin MSOP 24 9 PCB Land Pattern 14 pin SOIC Package 26 10 Electrical Characteristics 28 11 System Description 33 11 1 Overview 33 11 2 Setting Basic Si4010 Transmit Parameters 35 11 3 Applications Programming Interface API Commands 35 12 Power Amplifier 36 12 1 Register Description 38 13 Output Data Serializer ODS 40 13 1 Description 40 13 2 Timing 40 13 3 Register Description 41 14...

Page 4: ...ss 72 24 6 Error Handling During Boot 73 24 7 CODE XDATA RAM Address Map 73 24 8 Boot Status Variables 76 24 9 Boot Routine Destination Address Space 79 24 10 NVM Programming 80 24 11 Retest and Retest Configuration 81 24 12 Boot and Retest Protection NVM Control Byte 83 24 13 Chip Protection Control Register 84 25 On Chip Registers 85 25 1 Special Function Registers 85 25 2 XREG Registers 88 26 I...

Page 5: ...scription 129 34 Timers 2 and 3 131 34 1 Interrupt Flag Generation 132 34 2 16 bit Timer with Auto Reload Wide Mode 133 34 3 16 bit Capture Mode Wide Mode 133 34 4 8 Bit Timer Timer Mode Split Mode 134 34 5 8 Bit Capture Capture Mode Split Mode 135 34 6 8 Bit Timer Capture Mode Split Mode 136 35 C2 Interface 148 35 1 C2 Pin Sharing 148 36 IDE Development Environment and Debugging Chain 151 36 1 Fu...

Page 6: ...re 24 2 CODE XDATA RAM Address Map 75 Figure 24 3 Boot Routine Destination CPU Address Space for Copy from NVM 79 Figure 30 1 Device Package and Port Assignments 108 Figure 30 2 GPIO 3 1 Functional Diagram 110 Figure 30 3 Other GPIO Functional Diagram 110 Figure 30 4 Push Button Organization in Matrix Mode 113 Figure 30 5 GPIO 5 LED Driver Block Diagram 117 Figure 31 1 Output Clock Generator Block...

Page 7: ...stics 31 Table 10 6 Optional Crystal Oscillator Characteristics 31 Table 10 7 EEPROM Characteristics 32 Table 10 8 Low Power Oscillator Characteristics 32 Table 10 9 Sleep Timer Characteristics 32 Table 22 1 CIP 51 Instruction Set Summary 57 Table 24 1 Boot XDATA Status Variables 76 Table 24 2 Run Chip Retest Protection Flags NVM Programmer 81 Table 25 1 Special Function Register SFR Memory Map 85...

Page 8: ... OF XREG REGISTERS XREG Definition 12 2 wPA_CAP 38 XREG Definition 12 3 bPA_TRIM 39 XREG Definition 15 1 bLPOSC_TRIM 47 XREG Definition 16 1 bXO_CTRL 49 XREG Definition 17 3 IFC_COUNT 53 XREG Definition 23 1 abMTP_RDATA 16 68 ...

Page 9: ...SFR Definition 24 2 BOOT_FLAGS 78 NVM Byte Definition 24 3 PROT3_CTRL 83 SFR Definition 24 4 PROT0_CTRL 84 SFR Definition 26 1 IE 94 SFR Definition 26 2 IP 95 SFR Definition 26 3 EIE1 96 SFR Definition 26 4 EIP1 97 SFR Definition 26 5 INT_FLAGS 98 SFR Definition 26 6 PORT_INTCFG 100 SFR Definition 27 1 PCON 102 SFR Definition 28 1 GFM_DATA 104 SFR Definition 28 2 GFM_CONST 104 SFR Definition 28 3 ...

Page 10: ...tion 34 2 TMR2CTRL 140 SFR Definition 34 3 TMR2RL 142 SFR Definition 34 4 TMR2RH 142 SFR Definition 34 5 TMR2L 143 SFR Definition 34 6 TMR2H 143 SFR Definition 34 7 TMR3CTRL 144 SFR Definition 34 8 TMR3RL 146 SFR Definition 34 9 TMR3RH 146 SFR Definition 34 10 TMR3L 147 SFR Definition 34 11 TMR3H 147 ...

Page 11: ... General purpose input output pins with push button wake on touch capability a programma ble system clock and ultra low power timers are also available to further reduce current consumption The Si4010 includes Silicon Laboratories 2 wire C2 Debug and Programming interface This debug logic supports memory inspection viewing and modification of special function registers SFR setting break points sin...

Page 12: ...TEXREG 4KBYTERAM 12KBYTEROM DIGITALPERIPHERALS INTC RTC TMR2 3 AES128bACCEL GPIO0 XTAL VPP GPIO1 GPIO2 GPIO3 GPIO4 C2DAT GPIO5 C2CLK LED GPIO6 GPIO7 GPIO8 GPIO9 NVM 8KB EEPROM 128 bit MEMORY CONTROLLER 14PSOIC Package Only LCOSC PA DIVIDER XTAL OSC HVRAM 8Byte AUTO TUNE FSK OOK LPOSC TEMP SENSOR LDO POR BANDGAP VA VD TXP TXM VDD GND SLP TMR RFANALOGCORE ...

Page 13: ...st Circuit Figure 2 1 Test Block Diagram with 10 Pin MSOP U1 Si4010 GT GPIO0 GND TXM TXP VDD GPIO1 GPIO2 GPIO3 GPIO4 LED 1 2 3 4 5 10 9 8 7 6 C1 1 uF TESTER INTERFACE GP1 GP2 GP3 GP4 GP5 TEST EQUIPMENT GP0 VDD MATCHING NETWORK ...

Page 14: ...E System with LED Indicator Figure 3 2 Si4010 with an External Crystal in a 4 button RKE System with LED Indicator U1 Si4010 GT GPI0 GND TXM TXP VDD GPIO1 GPIO2 GPIO3 GPIO4 LED 1 2 3 4 5 10 9 8 7 6 CR2032 COIN CELL 1 8 to 3 6 V LOOP ANTENNA C1 1uF SW1 D1 SW0 SW2 SW3 SW4 C2 U1 Si4010 GT GPI0 GND TXM TXP VDD GPIO1 GPIO2 GPIO3 GPIO4 LED 1 2 3 4 5 10 9 8 7 6 CR2032 COIN CELL 1 8 to 3 6 V LOOP ANTENNA ...

Page 15: ...O with POR Circuit Low Battery Detector Automotive Qualified 3 Lead free RoHS Compliant Package Si4010 C2 GT 24 8k 4k Y 256 8 128 Y 5 1 Y Y Y Y Y MSOP 10 Si4010 C2 GS 24 8k 4k Y 256 8 128 Y 9 1 Y Y Y Y Y SOIC 14 Si4010 C2 AT 24 8k 4k Y 256 8 128 Y 5 1 Y Y Y Y Y Y MSOP 10 Si4010 C2 AS 24 8k 4k Y 256 8 128 Y 9 1 Y Y Y Y Y Y SOIC 14 Notes 1 Add an R at the end of the device part number to denote tape...

Page 16: ...iption Line 1 Circle 1 1 mm Diameter Left Justified e3 Pb Free Symbol Customer Part Number Si4010C2 Line 2 YY Year WW Work Week Assigned by the Assembly House Corresponds to the year and work week of the assembly date TTTTTT Trace Code Manufacturing code characters from the Markings section of the Assembly Purchase Order form ...

Page 17: ...nation Line Characters Description Line 1 Device Part Number 10C2 Line 2 TTTT Trace Code Line 2 from the Markings section of the Assembly Purchase Order form Line 3 YWW Date Code Date Code assigned by the assembly house Y Last Digit of Current Year Ex 2008 8 WW Work Week of Mold Date ...

Page 18: ...nput pin Can be configured as an input pin for a crystal 2 GND Ground Connect to ground plane on PCB 3 4 TXM TXP Transmitter differential outputs 5 VDD Power 6 LED Dedicated LED driver 7 8 9 10 GPIO 4 1 General purpose input output pins GPIO0 XTAL Si4010 GT 2 3 6 7 8 4 5 9 GPIO2 GPIO3 GPIO4 LED VDD TXP GND TXM 1 10 GPIO1 ...

Page 19: ...ND Ground Connect to ground plane on PCB 3 TXM Transmitter differential output 4 TXP Transmitter differential output 5 VDD Power 6 C2CLK C2 clock interface 7 C2DAT C2 data input output pin 8 9 10 GPIO 3 1 General purpose input output pins VPP GPIO0 XTAL Si4010 GT 2 3 6 7 8 4 5 9 GPIO2 GPIO3 C2DAT GPIO4 C2CLK LED VDD TXP GND TXM 1 10 GPIO1 ...

Page 20: ...crystal 3 GND Ground Connect to ground plane on PCB 4 5 TXM TXP Transmitter differential outputs 6 VDD Power 7 8 GPIO 7 6 General purpose input output pins 9 LED Dedicated LED driver 10 11 12 13 GPIO 4 1 General purpose input output pins 14 GPIO8 General purpose input output pin Si4010 GS 3 4 9 10 11 5 6 12 GPIO2 GPIO3 GPIO4 LED VDD GPIO0 XTAL TXP GND TXM 2 13 GPIO1 GPIO9 1 14 GPIO8 8 7 GPIO6 GPIO...

Page 21: ...und plane on PCB 4 5 TXM TXP Transmitter differential outputs 6 VDD Power 7 8 GPIO 7 6 General purpose input output pins 9 C2CLK C2 clock interface 10 C2DAT C2 data input output pin 11 12 13 GPIO 4 1 General purpose input output pins 14 GPIO8 General purpose input output pin Si4010 GS 3 4 9 10 11 5 6 12 GPIO2 GPIO3 C2DAT GPIO4 C2CLK LED VDD VPP GPIO0 XTAL TXP GND TXM 2 13 GPIO1 GPIO9 1 14 GPIO8 8 ...

Page 22: ...s Symbol Millimeters Min Nom Max Min Nom Max A 1 10 e 0 50 BSC A1 0 00 0 15 L 0 40 0 60 0 80 A2 0 75 0 85 0 95 L2 0 25 BSC b 0 17 0 33 q 0 8 c 0 08 0 23 aaa 0 20 D 3 00 BSC bbb 0 25 E 4 90 BSC ccc 0 10 E1 3 00 BSC ddd 0 08 Notes 1 All dimensions are shown in millimeters mm 2 Dimensioning and tolerancing per ASME Y14 5M 1994 3 This drawing conforms to JEDEC Outline MO 187 Variation BA 4 Recommended...

Page 23: ...s Symbol Min Max Symbol Min Max A 1 75 L 0 40 1 27 A1 0 10 0 25 L2 0 25 BSC b 0 33 0 51 Q 0 8 c 0 17 0 25 aaa 0 10 D 8 65 BSC bbb 0 20 E 6 00 BSC ccc 0 10 E1 3 90 BSC ddd 0 25 e 1 27 BSC Notes 1 All dimensions are shown in millimeters mm 2 Dimensioning and tolerancing per ASME Y14 5M 1994 3 This drawing conforms to JEDEC Outline MS012 variation AB 4 Recommended card reflow profile is per the JEDEC...

Page 24: ...Si4010 C2 24 Rev 1 0 8 PCB Land Pattern 10 Pin MSOP Figure 8 1 10 Pin MSOP Recommended PCB Land Pattern ...

Page 25: ... a Fabrication Allowance of 0 05mm Solder Mask Design 1 All metal pads are to be non solder mask defined NSMD Clearance between the solder mask and the metal pad is to be 60 m minimum all the way around the pad Stencil Design 1 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 2 The stencil thickness should be 0 125mm...

Page 26: ...Si4010 C2 26 Rev 1 0 9 PCB Land Pattern 14 pin SOIC Package Figure 9 1 14 Pin SOIC Recommended PCB Land Pattern ...

Page 27: ...rance between the solder mask and the metal pad is to be 60 µm minimum all the way around the pad Stencil Design 1 A stainless steel laser cut and electro polished stencil with trapezoidal walls should be used to assure good solder paste release 2 The stencil thickness should be 0 125 mm 5 mils 3 The ratio of stencil aperture to land pad size should be 1 1 for all perimeter pads Card Assembly 1 A ...

Page 28: ... Symbol Value Unit Supply Voltage VDD 0 5 to 3 9 V Input Current3 IIN 10 mA Input Voltage4 VIN 0 3 to VDD 0 3 V Junction Temperature TJ 40 to 90 C Storage Temperature TSTG 55 to 150 C Notes 1 Permanent device damage may occur if the absolute maximum ratings are exceeded Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet Exposure ...

Page 29: ...ll GPIO floating or held high 10 nA LED Sink Current ILED VOUT 200 mV 0 68 mA GPIO 0 9 Pull Up Resistance RPU 48 55 62 k High Level Input Voltage2 VIH Trip point at 0 45 x VDD 0 506 x VDD V Low Level Input Voltage2 VIL Trip point at 0 45 x VDD 0 42 x VDD V High Level Input Current2 IIH VIN VDD 10 µA Low Level Input Current2 IIL VIN 0 10 µA High Level Output Voltage3 VOH ISOURCE 500 µA 3 0 V Low Le...

Page 30: ... 2 V 10 dBm Minimum programmed TX power with optimum differen tial load VDD 2 2 V 13 dBm Power variation vs temp and supply with optimum differential load VDD 2 2 V 1 0 0 5 dB Power variation vs temp and supply with optimum differential load VDD 1 8 V 2 5 0 5 dB Transmit power step size from 13 to 10 dBm 0 25 dB PA Edge Ramp Rate Programmable Range OOK mode 0 34 10 7 us Data Rate OOK Manchester en...

Page 31: ...0 13 MHz Input Capacitance GPIO0 GPIO0 configured as a crystal oscillator XO_LOWCAP 1 3 pF GPIO0 configured as a crystal oscillator XO_LOWCAP 0 5 5 pF Crystal ESR GPIO0 configured as a crystal oscillator XO_LOWCAP 1 120 GPIO0 configured as a crystal oscillator XO_LOWCAP 0 80 Start up Time GPI00 configured as a crystal oscillator Crystal at Max ESR 9 50 ms Table 10 4 Si4010 RF Transmitter Character...

Page 32: ...Table 10 8 Low Power Oscillator Characteristics VDD 1 8 to 3 6 V TA 40 to 85 C unless otherwise specified Use factory calibrated settings Parameter Conditions Min Typ Max Units Programmable Frequency Range Programmable divider in powers of 2 up to 128 1875 24 MHz Frequency Accuracy 1 1 Table 10 9 Sleep Timer Characteristics VDD 1 8 to 3 6 V TA 40 to 85 C unless otherwise specified Use factory cali...

Page 33: ...rom the one time programmable OTP NVM to CODE XDATA RAM 4 kB because the MCU can only operate with programs stored in RAM or ROM The copy process occurs on each wake up event and requires approximately 2 ms of fixed time plus 3 6 ms per kB of data or 16 4 ms to fill the full 4 kB of CODE XDATA RAM After the NVM boot copy process is completed the MCU runs the user program in RAM and can also run fu...

Page 34: ...resistances the PA is current limited The PA tail current is programmable from 810 uA up to 7 67 mA in 0 25 dB steps and there is a boost current bit that multiplies the tail current by 1 5 times allowing it to go up to 11 5 mA With an antenna load resistance of about 500 an output power of 10 dBm is achievable Edge rate control is also included for OOK mode to reduce har monics that may otherwise...

Page 35: ...meters such as output power modulation type data rate and operating frequency are set by using applications programming interface API function commands When using these func tions certain parameters can be determined by using a calculator spread sheet The calculator spreadsheet is available through the Silicon Labs website www silabs com in the Support Document Library EZRadio section and it is pa...

Page 36: ...tic of the Si4010 for a differential loop antenna Application note AN369 Antenna Interface for the Si401x Transmitters provides detailed infor mation about designing the antenna interface for the Si401X transmitters With proper filtering and layout techniques the Si4010 can conform to US FCC part 15 231 and European EN 300 220 regulations Edge rate control is also included for OOK mode to reduce h...

Page 37: ...power Both the operating temperature and the capacitor tuning word are monitored by the chip and may be used to increase the nominal drive current to bring the product of the output voltage and driver capacitance back to what it was prior to the environmental change In order for this loop to operate cor rectly the parameters Alpha and Beta need to be determined from measured antenna characteristic...

Page 38: ...ias This parameter determines the bias current per slice of the PA Programming this register directly is not recommended Use the vPa_Setup API function instead XREG Definition 12 2 wPA_CAP Byte Offset 1 0 Name PA_CAP 1 0 Type R W Reset 0x00 0x00 Bit Name Function 1 0 PA_CAP 1 0 PA Variable Capacitance 9 bit linear control value of the output capacitance of the PA Accessed as 2 bytes word in big en...

Page 39: ... Reserved Reserved Type R W Reset 0 Bit Name Function 7 5 Unused 4 PA_MAX_ DRV PA MAX Drive Bit This parameter boost the bias current of the PA by 1 5 times up to 10 5 mA The values entered into this register come from the Power Amplifier Module API This bit should be set without changing the other bits 3 0 Reserved Reserved ...

Page 40: ...C oscillator to allow for FSK operation Provides test features to force on the power state of the LCOSC DIVIDER and PA recirculating a fixed pattern forcing the FSK offset frequency The SFR and XREG settings of this block are determined from the desired modulation data rate and encoding method and are automatically set by the ODS API in conjunction with the calculator Users are recommended to use ...

Page 41: ...ast bit 01 Reuse the last symbol group for transmission 10 All 0s data 11 All 1s data 5 FSK_ FORCE_ DEV Force FSK Deviation 0 Normal operation 1 Force the LCOSC to frequency deviate regardless of data pattern or FSK_MODE 4 FSK_MODE Selects Modulation Mode 0 OOK mode 1 FSK mode 3 FORCE_LC Force LCOSC On 0 Normal operation 1 Force LSCOSC on 2 FORC_DIV Force DIVIDER On 0 Normal operation 1 Force DIVI...

Page 42: ... end of a transmission which was previously using 8 symbol groups 4 3 ODS_ EDGE_ TIME 1 0 Controls PA Edge Time Additional division factor in range 1 4 ods_edge time 1 Edge rate 8 x ods_ck_div 1 ods_edge_time 1 24 MHz When clk_ods is in range of 3 8 MHz edge rate can be selected from 1us to 10 7 µs Study has indicated that in the worst case 20 kbps Manchester edge rates somewhat higher than 4 µs a...

Page 43: ...DS to notify the Tx ODS data SFR holding register been written to and contains new data The pulse is a registered write pulse so it will be generated when the data is stable in the holding register ODS data format is little endian SFR Definition 13 4 ODS_RATEL Bit 7 6 5 4 3 2 1 0 Name ODS_RATEL 7 0 Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 ODS_RATEL 7 0 Lower...

Page 44: ...mis sion or on the transition from OOK Zero bit to OOK One bit Set this value in a way that the warm up interval of the divider should be 5us for a given ODS clock rate Interval is in 4 x clk_ods cycles resolution Interval 4 x ods_warm_div x ods_ck_div 1 24 MHz Using the Si4010 calculator spreadsheet in order to determine the correct value of this parameter is strongly recommended 3 0 ODS_ WARM_ P...

Page 45: ... Sets the warm up interval for the LC oscillator where it is biased up prior to transmission or on the transition from OOK zero bit to OOK one bit Set this value in a way that the warm up interval of the LCOSC should be 125 µs for a given ODS clock rate Interval is in 64 x clk_ods cycles resolution Interval 64 x ods_warm_lc x ods_ck_div 1 24 MHz Using the Si4010 calculator spreadsheet in order to ...

Page 46: ...l temperature range of 0 to 70 C and 250 ppm frequency stability over the industrial temperature range of 40 to 85 C The transmit carrier frequency is set by using the API functions vFCast_Tune desired carrier and vFCast_Setup For FSK modulation the frequency deviation is also a parameter to the freq_adjustment function Users are recommended to use the API functions to set the corresponding SFR re...

Page 47: ...to all digital blocks including the MCU and is program mable via the SYSGEN SFR register which is useful for power savings Users are recommended to use the System Module Function API to set the registers 15 1 Register Description XREG Address 0x4002 XREG Definition 15 1 bLPOSC_TRIM Bit 7 6 5 4 3 2 1 0 Name LPOSC_TRIM 7 0 Type R W Reset 1 1 1 1 1 1 1 1 Bit Name Function 7 0 LPOSC_ TRIM 7 0 Low Powe...

Page 48: ...ead as 0 Write has no effect 5 PWR_1ST_ TIME Initial Powerup Indicator Read only register It will get set when power up was caused by a battery insertion 4 RTC_ TICKCLR Real Time Clock Clear 0 Normal operation 1 Clears the real time clock 5 12us counter 3 PORT_ HOLD Port Hold This bit needs to be set before shutting down it delays any button pushes that occur between this bit setting and shutdown ...

Page 49: ...apacitance of the XTAL pin of the Si4010 is approximately 5 5 pF so a Cload 5 5 pF capacitor should be placed externally across the crystal terminals If Cload 14 pF XO_LOWCAP bit of the bXO_CTRL register have to be set to 1 In this case the input capacitance of the XTAL pin of the Si4010 is approximately 3 pF so the external capacitor placed across the crystal has to be Cload 3 pF 16 1 Register De...

Page 50: ...nter has to be triggered by writing 1 to the FC_BUSY bit By writing FC_BUSY 1 the FC_DONE bit gets cleared as well The user can also clear the FC_DONE bit in software after reading the main FC_COUNT value Once the interval counter is triggered and after several clk_sys cycles synchronization delay it waits for the first rising edge of the clk_int clock which is the output of the interval counter c...

Page 51: ...er of interval count cycles count cycles of the low frequency clock 2 FC_INTERVAL 0 2 FC_INTERVAL 5 1 Note FC_INTERVAL is not allowed to take on numbers higher than 43 If the number is higher than 43 then the calculated number or interval count cycles is forced to 1 Even though 43 is the maximum FC_INTERVAL setting lower FC_INTERVAL settings can cause the 23 bit frequency counter to overflow depen...

Page 52: ...DONE 1 Writing 1 to this bit triggers a new FC counting cycle FC is restartable so any Wr 1 to this bit restarts the FC and discards what the FC was currently doing 0 Frequency counter is not busy falling edge sets FC_DONE 1 1 Writing 1 restarts the Frequency Counter 5 FC_DIV_ SEL Frequency Counter Divider Select Selection control of source of clock It chooses between LC and DIVIDER If the fre que...

Page 53: ... 2 fcnt_interval 5 1 Note that fcnt_interval is allowed to take on values no higher than 43 If the number higher than 43 is used then the the interval counted is forced to n_cycles 1 XREG Definition 17 3 IFC_COUNT Bit 3 2 1 0 Name IFC_COUNT 3 0 Type R Reset 0x00 0x00 0x00 0x00 Bit Name Function 3 0 IFC_COUNT 0 3 Frequency Counter Output Counter output value Accessed as 4 bytes long word in big end...

Page 54: ...tors the power applied to the chip and generates a reset signal to set the chip into a known state The bandgap produces voltage and current references for the analog blocks in the chip and can be shut down when the analog blocks are not used Control of the bandgap and LDO is done with the System Module Function API vSys_BandGapLdo 20 Low Leakage HVRAM The low leakage HVRAM provides 8 bytes of RAM ...

Page 55: ...re In a standard 8051 all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute and usually have a maximum system clock of 12 MHz By contrast the CIP 51 core executes 70 of its instructions in one or two system clock cycles with no instructions taking more than eight system clock cycles Figure 22 1 CIP 51 Block Diagram l Fully Compatible with MCS 51 Instruction Set l 24 ...

Page 56: ... of the stan dard 8051 22 1 1 Instruction and CPU Timing In many 8051 implementations a distinction is made between machine cycles and clock cycles with machine cycles varying from 2 to 12 clock cycles in length However the CIP 51 implementation is based solely on clock cycle timing All instruction timings are specified in terms of clock cycles Due to the pipelined architecture of the CIP 51 most ...

Page 57: ... INC Ri Increment indirect RAM 1 2 DEC A Decrement A 1 1 DEC Rn Decrement register 1 1 DEC direct Decrement direct byte 2 2 DEC Ri Decrement indirect RAM 1 2 INC DPTR Increment Data Pointer 1 1 MUL AB Multiply A and B 1 4 DIV AB Divide A by B 1 8 DA A Decimal adjust A 1 1 Logical Operations ANL A Rn AND Register to A 1 1 ANL A direct AND direct byte to A 2 2 ANL A Ri AND indirect RAM to A 1 2 ANL ...

Page 58: ...rect RAM 1 2 MOV Ri direct Move direct byte to indirect RAM 2 2 MOV Ri data Move immediate to indirect RAM 2 2 MOV DPTR data16 Load DPTR with 16 bit constant 3 3 MOVC A A DPTR Move code byte relative DPTR to A 1 3 MOVC A A PC Move code byte relative PC to A 1 3 MOVX A Ri Move external data 8 bit address to A 1 3 MOVX Ri A Move A to external data 8 bit address 1 3 MOVX A DPTR Move external data 16 ...

Page 59: ...Return from subroutine 1 5 RETI Return from interrupt 1 5 AJMP addr11 Absolute jump 2 3 LJMP addr16 Long jump 3 4 SJMP rel Short jump relative address 2 3 JMP A DPTR Jump indirect relative to DPTR 1 3 JZ rel Jump if A equals zero 2 2 3 JNZ rel Jump if A does not equal zero 2 2 3 CJNE A direct rel Compare direct byte to A and jump if not equal 3 4 5 CJNE A data rel Compare immediate to A and jump i...

Page 60: ...ould be a direct access Data RAM location 0x00 0x7F or an SFR 0x80 0xFF data 8 bit constant data16 16 bit constant bit Direct accessed bit in Data RAM or SFR addr11 11 bit destination address used by ACALL and AJMP The destination must be within the same 2 kB page of program memory as the first byte of the following instruction addr16 16 bit destination address used by LCALL and LJMP The destinati...

Page 61: ...the feature s default state Detailed descriptions of the remaining SFRs are included in the sec tions of the data sheet associated with their corresponding system function SFR Address 0x82 SFR Address 0x83 SFR Definition 22 1 DPL Bit 7 6 5 4 3 2 1 0 Name DPL 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 DPL 7 0 Data Pointer Low The DPL register is the low byte of the 16 bit DPTR SFR Def...

Page 62: ...0 SP 7 0 Stack Pointer The Stack Pointer holds the location of the top of the stack The stack pointer is incre mented before every PUSH operation The SP register defaults to 0x07 after reset SFR Definition 22 4 ACC Bit 7 6 5 4 3 2 1 0 Name ACC 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 ACC 7 0 Accumulator This register is the accumulator for arithmetic operations ...

Page 63: ...dress 0xF0 Bit Addressable SFR Definition 22 5 B Bit 7 6 5 4 3 2 1 0 Name B 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 B 7 0 B Register This register serves as a second accumulator for certain arithmetic operations ...

Page 64: ...eral purpose flag for use under software control 4 3 RS 1 0 Register Bank Select These bits select which register bank is used during register accesses 00 Bank 0 Addresses 0x00 0x07 01 Bank 1 Addresses 0x08 0x0F 10 Bank 2 Addresses 0x10 0x17 11 Bank 3 Addresses 0x18 0x1F 2 OV Overflow Flag This bit is set to 1 under the following circumstances l An ADD ADDC or SUBB instruction causes a sign change...

Page 65: ...es can be byte addressable or bit address able Apart from the CPU core related internal memory the device has the following memories 4 5 kB of RAM it can be used both as program CODE and external data XDATA memory 12 kB of ROM it holds the Silicon Labs provided API Application Programming Interface routines The ROM is not readable by the user 256B hardware control registers mapped to XDATA address...

Page 66: ...pace The addressing mode used by an instruction when accessing locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs Instructions that use direct addressing will access the SFR space Instructions using indirect addressing above 0x7F access the upper 128 bytes of data memory Figure 23 1 illustrates the data memory organization 23 3 External Da...

Page 67: ...change with the CIP 51 s resources and peripherals The CIP 51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub systems unique to the MCU This allows the addition of new functionality while retaining compatibility with the MCS 51 instruction set Table 25 1 lists the SFRs implemented in the device The SFR register...

Page 68: ...ly a single bit is to be changed in MTP the current content must be copied to the CODE XDATA RAM in full all 16 bytes Then the desired bit has to be changed in that RAM copy and an API function has to be called to program the 16 byte changed data from RAM to MTP The user can use the API MTP copy call to get the current content of MTP into CODE XDATA RAM for modifications If the MTP bit is not chan...

Page 69: ...d data is copied from NVM to the CODE XDATA RAM Only after the boot process finishes the user code starts being executed from CODE XDATA RAM address 0x0000 Therefore upon reset the device does not execute the user code immediately but only after the boot pro cess finishes The time in between the device wakeup either caused by cycling the power or waking up from the shutdown mode by button press de...

Page 70: ... The part can be used with IDE for further software development The part is still opened for further NVM programming and the user can add additional data to the User region in the NVM Debugging of the code loaded from NVM is possible The user can modify the boot behavior of the User part by controlling two bits described later in the boot sequence description This program level can be used two way...

Page 71: ...sed on the user application request Application note will be devoted to this technique 4 Reserved region last 64 bytes of NVM are reserved for factory use and not available for user load The User load can occupy the rest of the NVM The user may decide that he will use overlays That means that the boot routine will not copy all the data from NVM to RAM upon boot but during the runtime of the user p...

Page 72: ...ng chain and IDE this is taken care of automatically by the IDE and there is no user intervention required 4 If the program level is User then the same procedure is followed as for the Factory device After that the boot procedure automatically see Note 1 continues to load User region from NVM to CODE XDATA RAM and IRAM After it finishes the device does not execute any code see Note 2 and goes to t...

Page 73: ...ss range 0x0000 0x11FF is the main area for the user program CODE and external data XDATA It is a unified memory referred to as CODE XDATA RAM in this docu ment so both CPU code CODE can be executed there and external data XDATA can reside there External data are the data accessible by MOVX instructions MOVC instructions can also be used to access data in that region After the boot of a Run part t...

Page 74: ...ammed into the NVM PROT3_CTRL internal byte in the Factory region of the NVM controlling the boot process It contains all the user code protection bits and modification of the User part boot process wBoot_NvmUserBeg address in NVM of the beginning of the User load For programming the User load into the NVM the NVM programming utility has to be properly configured by using this value The value is r...

Page 75: ...DATA RAM Address Map Boot_AfterTrimExe Boot_PatchExe R e s e r v e d Boot XDATA 0x0000 Factory XDATA bBoot_BootStat wBoot_NvmCopyAddr wBoot_NvmUserBeg wBoot_DpramTrimBeg User CODE XDATA 0x11FF 0x11FD 0x11F3 0x11F5 CODE XDATA RAM 4 5KB 0x11F7 ...

Page 76: ... the very beginning of the boot before the XO was optionally turned on Table 24 1 Boot XDATA Status Variables Register Addr Type Description wBoot_DpramTrimBeg 0x11F3 WORD Address of the first occupied byte by the Silicon Labs factory data in CODE XDATA RAM This variable is set after the boot User must read the variable to determine where is the end of the usable CODE XDATA RAM mem ory for user s ...

Page 77: ...owever if the user wants to make the User part to behave as a Factory part then it is possible to write value 0x20 to the BOOT_FLAGS register through IDE see View Debug Windows SFR Boot window Don t forget to press the Refresh IDE button for the change to take effect Then until the power to the part is cycled the part would behave as a Factory part XDATA Variable Definition 24 1 bBoot_BootStat Bit...

Page 78: ...POR Run User Code in RAM Same functionality as CODE_RUN_SYS 3 Reserved Reserved 2 BOOT_ FAIL_ SYS Boot Loading Process Failed This is an information flag independent of the BOOT_DONE_SYS This bit is set when the boot status XDATA variable bBoot_BootStat is not equal to 0x00 signal ling error during boot It is recommended that the user code reads this bit and possibly make decisions whether to cont...

Page 79: ...tination address in the NVM image is in this region the data destination is going to be DATA IDATA IRAM space However only region 0x7020 0x70EF is writable That means that the first 32 and last 16 bytes of the IRAM are not writable by a boot process Note that the mapping is for indirect internal IRAM access DATA IDATA so SFR registers cannot be initialized by this process It is up to the user to g...

Page 80: ...ramming process the user will have control of the following 1 Make Factory part a User part program User data into the NVM 2 Update User part add additional User data block to the existing User data already in NVM This process can be done many times as long as there is a space in NVM 3 Make User part a Run part mark a part as a final mission mode part When making the part a Run part the user can d...

Page 81: ...s are completed can the chip open for retest communication When making a Run part the user can set the following retest protection flags when using the NVM programmer Note that if the bits are set into the PROT3_CTRL NVM byte before the part is programmed as Run part for example those bits are set when making a User part the settings are ignored The boot process will monitor these values only afte...

Page 82: ...c2_prot Protect NVM When set then both Wr and Rd access to NVM is disabled It forces boot process to write NVM_PROT 1 at the end of the boot process to disable NVM access This protects User load in NVM from being read by SiLabs If this option is used then the SiLabs can still do the following with NVM content during retest 1 Calculate CRC32 over the Factory region of NVM 2 Calculate CRC32 over the...

Page 83: ...Entering Retest Mode This bit corresponds to MTP Disable checkbox on the NVM programmer GUI 5 MEM_C2_ PROT RAM Clearing Content Protection When Entering Retest Mode This bit corresponds to RAM Clear checkbox on the NVM programmer GUI 4 BOOT_XO_ ENA Enable the Crystal Oscillator XO at the Beginning of the Boot Process This is valid in any device programming level including Factory Since it can take...

Page 84: ...pe R W R W R R W R W R W R W R W Reset 0 0 1 0 0 0 0 0 Bit Name Function 7 NVM_ PROT NVM Protection Disable NVM access completely Neither read nor write to NVM is possible Write 1 sets the bit write 0 has no effect 6 C2_OFF C2 Interface Disable Write 1 sets the bit write 0 has no effect This bit is reset by the main digital power on reset Power has to be cycled to reset this bit or chip has to wak...

Page 85: ... memory locations from 0x80 to 0xFF SFRs with addresses ending in 0x0 or 0x8 e g P0 P1 ACC IE etc are bit address able as well as byte addressable All other SFRs are byte addressable only Unoccupied addresses in the SFR space are reserved for future use Accessing these areas will have an indeterminate effect and should be avoided Refer to the corresponding pages of the data sheet as indicated in T...

Page 86: ...04 GFM_DATA 0x84 AES GFM Data 104 GPR_CTRL 0xB1 General Purpose Control Register 126 GPR_DATA 0xB2 General Purpose Data Register 126 IE 0xA8 Interrupt Enable 94 IP 0xB8 Interrupt Priority 95 INT_FLAGS 0xBF Interrupt Flags 98 LC_FSK 0xE4 LC FSK Deviation 46 ODS_CTRL 0xA9 ODS Control 41 ODS_DATA 0xAB ODS Data 43 ODS_RATEH 0xAD ODS Rate High Byte 44 ODS_RATEL 0xAC ODS Rate Low Byte 43 ODS_TIMING 0xAA...

Page 87: ...C8 Timer Counter 2 Control 140 TMR2H 0xCD Timer Counter 2 High 143 TMR2L 0xCC Timer Counter 2 Low 143 TMR2RH 0xCB Timer Counter 2 Reload High 142 TMR2RL 0xCA Timer Counter 2 Reload Low 142 TMR3CTRL 0x91 Timer Counter 3Control 144 TMR3H 0x95 Timer Counter 3 High 147 TMR3L 0x94 Timer Counter 3Low 147 TMR3RH 0x93 Timer Counter 3 Reload High 147 TMR3RL 0x92 Timer Counter 3 Reload Low 146 TMR_CLKSEL 0x...

Page 88: ... integers for example On the other hand the SFR register access is faster and one can use arithmetic and logical operations on them Note registers in the XREG regions are aligned at 8 16 and 32 bit boundaries and they are stored in big endian fashion This is to support Keil C compiler which uses big endian Note that if the register is say 23 bits wide the 32 bits 4 bytes are allocated for the regi...

Page 89: ...rved 0x4008 0x4009 0x400a 0x400b LWORD IFC_COUNT 0x400c 0x400d WORD wPA_CAP 0x400e 0x4011 reserved 0x4012 BYTE bPA_TRIM 0x4013 0x4015 reserved 0x4016 BYTE bXO_CTRL 0x4017 BYTE bPORT_TST 0x4018 0x4026 reserved 0x4040 0x404f BYTE abMTP_RDATA 16 Note Multiple byte variables if they are not arrays are stored in big endian MSB byte stored on lower address Arrays are stored with byte index 0 at lower ad...

Page 90: ...its and less then 16 it occupies two bytes That s why the prefix letter w denoting a two byte WORD The bits 15 9 are read as all zeros and write has no effect They are aligned towards MSB byte of the wPA_CAP the one at lower address since the byte ordering is in big endian fashion Table 25 4 XREG Registers XREGs are listed in alphabetical order Register Address Description Page lFC_COUNT 0x4008 Fr...

Page 91: ...idual interrupt enables are recog nized Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt enable set tings Note that interrupts which occur when the EA bit is set to logic 0 will be held in a pending state and will not be serviced until the EA bit is set back to logic 1 Note Any instruction that clears a bit to disable an interrupt should be immedi...

Page 92: ...vel Low priority is the default If two interrupts are recognized simultaneously the interrupt with the higher priority is serviced first If both interrupts have the same priority level a fixed priority order is used to arbitrate given in Table 26 1 26 3 Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs Pending interrupts are sampled and priority de...

Page 93: ...low 0x000B 1 TMR2INTL TMR2CTRL 6 TMR2INTH TMR2CTRL 7 Y ETMR2 IE 1 PTMR2 IP 1 Temp Sensor DMD 0x0013 2 DMD_NEW DMD_CTRL 3 N EDMD IE 2 PDMD IP 2 Real Time Clock Tick 0x001B 3 RTC_INT RTC_CTRL 7 N ERTC IE 3 PRTC IP 3 ODS Ready for Data 0x0023 4 ODS_FLAG INT_FLAGS 2 N EODS IE 4 PODS IP 4 Timer 3 Overflow 0x002B 5 TMR3INTL TMR3CTRL 6 TMR3INTH TMR3CTRL 7 N ETMR3 IE 5 PTMR3 IP 5 External INT1 0x0033 6 IN...

Page 94: ... of the Timer 3 interrupt 0 Disable Timer 3 interrupt 1 Enable interrupt requests generated by the TF3L or TF3H flags 4 EODS Enable Output Data Serializer Interrupt This bit sets the masking of the ODS interrupt 0 Disable ODS interrupt 1 Enable ODS interrupt 3 ERTC Enable Real Time Clock Interrupt This bit sets the masking of the RTC interrupt 0 Disable all RTC interrupt 1 Enable RTC interrupt 2 E...

Page 95: ...ority Control This bit sets the priority of the ODS interrupt 0 ODS interrupt set to low priority level 1 ODS interrupt set to high priority level 3 PRTC Real Time Clock Interrupt Priority Control This bit sets the priority of the RTC interrupt 0 RTC interrupt set to low priority level 1 RTC interrupt set to high priority level 2 PDMD DMD TS demodulator Interrupt Priority Control This bit sets the...

Page 96: ...e VOID1 interrupt Reserved 0 Disable VOID1 interrupts 1 Enable interrupt requests generated by VOID1 flags Reserved 3 EVOID0 Enable VOID0 Interrupt Reserved This bit sets the VOID0 interrupt Reserved 0 Disable VOID0 interrupts 1 Enable interrupt requests generated by VOID0 flags Reserved 2 EFC Enable Frequency Counter Interrupt This bit sets the Frequency Counter interrupt 0 Disable Frequency Coun...

Page 97: ...rrupt set to low priority level 1 VOID1 interrupt set to high priority level 3 PVOID0 VOID0 Interrupt Priority Control This bit sets the priority of the VOID0 interrupt 0 VOID0 interrupt set to low priority level 1 VOID0 interrupt set to high priority level 2 PFC Frequency Counter Interrupt Priority Control This bit sets the priority of the Frequency Counter interrupt 0 Frequency Counter interrupt...

Page 98: ... Spare Interrupt Flag can be used freely by the user application software Interrupt can be invoked by software only by writing 1 here 2 ODS_ FLAG Set when TX Data Holding Register becomes Empty It must be cleared by software BEFORE writing a new byte into the ODS Tx data register Hardware will not clear this bit 1 INT1_ FLAG Set by Selected GPIO Input by a Selected Edge It gets set irrespective of...

Page 99: ...not automatically cleared by the hardware when the CPU vec tors to the ISR This is a departure from the original 8051 architecture where if external interrupts were configured to be edge sensitive the corresponding interrupt flag was cleared by hardware upon the exit from the ISR routine The detection of the edges of INT0 and INT1 sources is done by sampling the associated port inputs by the inter...

Page 100: ...election Bits These bits select which Port pin is assigned to INT1 000 Select GPIO0 001 Select GPIO1 010 Select GPIO2 011 Select GPIO3 100 Select GPIO4 101 Select GPIO9 110 Select GPIO6 111 Select GPIO7 3 NEG_ INT0 Negative INT0 Polarity This bit selects whether the selected INT0 GPIO input will get inverted or pass as is before going to the edge detector Note the edge detector detects either the ...

Page 101: ...emain active during Idle mode Idle mode is terminated when an enabled interrupt or reset is asserted The assertion of an enabled inter rupt will cause the Idle Mode Selection bit PCON 0 to be cleared and the CPU to resume operation The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt RETI will be the instruction immediately following the on...

Page 102: ...r use under software control 1 STOP Stop Mode Select Setting this bit will place the CIP 51 in Stop mode This bit will always be read as 0 1 CPU goes into Stop mode internal oscillator stopped 0 IDLE Idle Mode Select Setting this bit will place the CIP 51 in Idle mode This bit will always be read as 0 1 CPU goes into Idle mode Shuts off clock to CPU but clock to Timers Interrupts Serial Ports and ...

Page 103: ...A register invokes the actual multiply operation It takes 2 system clock cycles to perform the multiplication and the calculated result appears in the GFM_DATA register overwriting the user input data Therefore at least a single cycle dummy instruction must be added in between writing the data to be multiplied to the GFM_DATA register and reading the result from there mov GFM_DATA data Invoke a GF...

Page 104: ...sters the data for processing Processed data is regis tered into the same register with single CLK_SYS cycle delay Read from this reg ister reads the processed multiplied data The register GFM_CONST must be written before GFM_DATA is written Bit 7 6 5 4 3 2 1 0 Name GFM_CONST 7 0 Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 GFM_CONST 7 0 GFM Multiplier Constant ...

Page 105: ...egister with single CLK_SYS cycle delay Read from this reg ister reads the processed data The type of SBox processing is controlled by AES_DECRYPT bit Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved AES_DECRYPT Reserved Reserved Reserved Type R W R W R W R W R W R W R W R W Reset 0 0 0 1 0 0 0 0 Bit Name Function 7 5 Reserved Reserved Read as 0x0 Write has no effect 4 Reserved Reserve...

Page 106: ... Device starts its startup boot procedure See other sections for descrip tion of the boot procedure The user code starts being executed only after the boot procedure finishes See section 24 System Boot and NVM Programming for details 29 1 Device Boot Outline Since the device does not have flash memory to permanently hold user code the device has to go through a boot sequence in which the user code...

Page 107: ...en putting the device into shutdown mode This action effective disconnects power to the internal systems of the device Once the sleep time expires it will wake the Si4010 which will have the same effect as a power on reset to the device creating a software reset Note that the sleep timer must be programmed and armed before the user puts the devices into shutdown mode ...

Page 108: ...ttom bits of Port 0 14 pin package 10 port pins organized as a full 8 bit Port 0 and 2 bottom bits of Port 1 The package pin assignment is in Figure 30 1 Figure 30 1 Device Package and Port Assignments 8 9 10 11 12 13 14 7 6 5 4 3 2 1 GD TXM TXP VDD 10 pin package GPIO 9 GPIO 0 XO VPP GPIO 7 GPIO 1 MatDrv Roff GPIO 2 MatDrv Roff GPIO 3 MatDrv GPIO 4 C2DAT GPIO 5 LED C2CLK GPIO 6 GPIO 8 ...

Page 109: ... related digital control are in Figure 30 2 and Figure 30 3 The option for Matrix mode is available only on GPIO 3 1 and the option for Roff mode is available only on GPIO 2 1 Table 30 1 10 Pin Mode Package Pin Number Package Pin Name 1 GPIO0 XO 10 GPIO1 9 GPIO2 8 GPIO3 7 GPIO4 6 GPIO5 LED Table 30 2 14 Pin Mode Package Pin Number Package Pin Name 2 GPIO0 XO 13 GPIO1 12 GPIO2 11 GPIO3 10 GPIO4 9 G...

Page 110: ...ed functionality e g as input only etc Figure 30 3 Other GPIO Functional Diagram Vcc GPIO n gpio_dataout n gpio_push_pull n gpio_in n port_dataout n port_oe n port_push_pull n GPIO Pads Digital logic Rd PORT_MATRIX Rd PORT_ROFF E E 2 3 2 PORT_STROBE Wr PORT_ROFF Wr PORT_MATRIX 50k 1 Vcc GPIO n gpio_dataout n gpio_push_pull n gpio_in n port_dataout n port_oe n port_push_pull n GPIO Pads Digital log...

Page 111: ...terface C2CLK In the development system the LED has to be isolated from the pin as shown in Figure 35 1 and Figure 35 2 The LED is disabled during debugging Table 30 3 GPIO Special Roles GPIO Number Other Special Roles C2 FOB Can Drive Low During Sleep Pullup Roff Option 0 XO VPP11 button 1 button Y Y 2 button Y Y 3 clk_ref2 button Y 4 clk_out out C2DAT button 5 C2CLK LED3 6 14 pin only clk_out ou...

Page 112: ... to some output GPIO the output GPIO must be connected to ground during the chip shutdown That is achieved by setting the Matrix option control bit in the GPIO latch When that bit is set then the GPIO 3 1 are actively pulled to ground when the chip is in the shutdown mode and digital logic has no power internally Note that to use the Matrix mode the Roff option must not be used In other words all ...

Page 113: ...i4010 C2 Figure 30 4 Push Button Organization in Matrix Mode Pushbuttons connecting the crossing wires GPIO 4 GPIO 1 GPIO 2 GPIO 3 E PORT_STROBE Wr PORT_MATRIX GPIO 0 GPIO 6 GPIO 7 GPIO 8 GPIO 9 14 pin package only ...

Page 114: ...r PORT_STROBE 0 Using Silicon Labs provided masks in the header anl PORT_CTRL NOT M_PORT_MATRIX OR M_PORT_ROFF orl PORT_CTRL M_PORT_STROBE anl PORT_CTRL NOT M_PORT_STROBE The toggle of the PORT_STROBE from 0 to 1 back to 0 latches the current register values of PORT_MATRIX and PORT_ROFF To summarize To change the values of the Matrix an Roff options the following software sequence is required 1 Se...

Page 115: ...serves multiple purposes Special configuration registers PORT_CTRL and PORT_SET are used to configure GPIO for other purpose then regular GPIO Some GPIO can server multiple special purposes Table 30 4 shows all the functionality the GPIO can assume along with control signals and priority of the functionality The lower the priority number the higher the functional priority For example if the functi...

Page 116: ...Output clk_out 2 PORT_SET PORT_CLKEN PORT_SET PORT_CLKOUT 0 Cannot be used in the development system since C2 transaction disrupts the output GPIO 3 P0 4 P0CON 4 5 C2CLK 1 Acts as if a C2 debug clock input of the LED driver is not turned on LED driver 2 P0 5 PORT_CTRL PORT_LED 1 0 Port forced as output To read the actual LED driver status on off the user should read RBIT_DATA GPIO_LED_DRIVE 6 Outp...

Page 117: ...y During the C2 debug sessions the IDE will forcibly disable the LED driver so the LED drive will not interfere with the debugging session There will be an option on IDE to disable the LED disable but it will have to be used with caution When the user hits Disconnect button on the IDE then the IDE clears all breakpoint removes the LED dis able and runs the application from the point where it was h...

Page 118: ... logic high value Special pins The GPIO 0 is input only Write to GPIO 0 has no effect The GPIO 5 is output LED driver only and requires setting of the proper LED drive current Then GPIO 5 just turns the LED current on 1 or off 0 Reading from GPIO 5 returns the user intended driver of LED 1 driving 0 off The read value will be read as 0 if for example the user writes GPIO 5 as 1 but the LED current...

Page 119: ... in P0 0 open drain 1 push pull If the pin to be input it must be configured as open drain and 1 has to be written as output value to it SFR Definition 30 3 P1 Bit 7 6 5 4 3 2 1 0 Name P1 7 0 Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 1 1 Bit Name Function 7 0 P1 7 0 Port 1 Register GPIO 15 8 Bit Addressable Write appears at the GPIO 15 8 outputs read reads directly the GPIO input valu...

Page 120: ...d If the pin to be input it must be configured as open drain and 1 has to be written as output value to it Only bits 1 0 corresponding to GPIO 9 8 are used write to the rest of the register has no effect read returns 0 for those bits SFR Definition 30 5 P2 Bit 7 6 5 4 3 2 1 0 Name P2 7 0 Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 P2 7 0 Port 2 Register Bit Add...

Page 121: ...tched into the GPIO pad internal Roff mode HV latch then the GPIO Roff mode gets invoked The GPIO 1 2 will have their pull up resistors turned off 5 PORT_ MATRIX Port Matrix Mode Matrix mode read from this bit returns the actual value matrix mode value as reported from GPIO pad When a 1 is latched into the GPIO pad internal matrix mode HV latch then the GPIO matrix mode gets invoked The GPIO 1 3 a...

Page 122: ..._CLKOUT 0 1 clk output at GPIO 4 0 normal other GPIO 4 operation PORT_CLKOUT 1 1 clk output at GPIO 6 0 normal other GPIO 6 operation Both outputs can be used simultaneously The actual clock waveform can be enabled disabled by port_clken bit but the GPIO configuration is purely controlled by PORT_CLKOUT 3 PORT_ CLKEN Enable Output Clock Which is Possibly Coming out on GPIO 4 and or GPIO 6 This bit...

Page 123: ...4kHz The divider has an option to keep the clk_out duty cycle to 1 1 even for odd division ratios There is an option of at which logic level the clk_out stops when the clock generator is disabled The clock divider generator always finishes the period it started before it accepts a new division factor CLKOUT_DIV It is recommended to fix all the settings before enabling the output clock generator Th...

Page 124: ...uld use this bit to synchronously switch the CLKOUT_DIV division factor but it is not necessary The synchronous clock period switching is built in the hard ware See the CLKOUT_DIV field description of this register To switch the clocks immediately without waiting for the current period to end write 1 to this bit The write 1 to this bit can be combined with setting the new CLKOUT_DIV value in this ...

Page 125: ...f the clock is controlled by the PORT_CLKEN and PORT_CLKOUT bits in PORT_SET register The division factors 0 and 1 pass the 24 MHz internal cheap oscillator output as output clocks Value bigger than 1 is the actual division factor of the 24 MHz If CLKOUT_SYM 0 recommended the generated clock is an output of a flop For odd division ratios the first part of the period in logic 0 is one 24 MHz clock ...

Page 126: ...y do not con trol any hardware on the device SFR Address 0xB1 SFR Address 0xB2 SFR Definition 32 1 GPR_CTRL Bit 7 6 5 4 3 2 1 0 Name GPR_CTRL 7 0 Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 GPR_CTRL 7 0 General Purpose Register SFR Definition 32 2 GPR_DATA Bit 7 6 5 4 3 2 1 0 Name GPR_DATA 7 0 Type R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bit Name ...

Page 127: ...0 5 bit is read then it returns user LED drive request which does not reflect the actual LED driver status 4 XO_CKGOOD Crystal Oscillator Clock Good Crystal oscillator XO output is stable 3 ODS_EMPTY ODS Empty Supplementary flag indicating that the ODS Tx holding register is empty It can be used as an indication for software to write a new data byte to ODS_DATA register to transmit This applies to...

Page 128: ...ision of the 24 MHz internal oscillator The frequency ranges from 24 MHz down to 24 MHz 128 The RTC tick generated is a constant frequency of 24 MHz 128 with tick period 5 33 µs and is independent of the system clock division setting SYSGEN_DIV in the SYSGEN SFR register The user can select what exact time intervals the RTC timer will set its interrupt flag The time interval is programmable to be ...

Page 129: ... 2 Register Description The RTC timer is controlled by the RTC_CTRL SFR register If there is a need for precise beginning of the RTC timer period the internal tick generator can be cleared by writing a bit RTC_TICKCLR in the SYSGEN register The rtc_tick generator runs freely whenever the RTC timer is enabled by RTC_ENA 1 If the user needs to clear the RTC timer to synchronize it with some event wr...

Page 130: ...nerator starts running where it left off If RTC_DIV 3 then top half also starts 0 RTC disabled 1 RTC enabled 5 RTC_CLR Real Time Clock Clear Writing 1 will clear the pulse generator but will leave the RTC_TICK generator intact See the RTC_TICKCLR in the SYSGEN register for clearing the RTC_TICK counter 0 Normal operation 1 RTC cleared 4 3 Reserved Read as 0x00 Write has no effect 2 0 RTC_DIV 2 0 R...

Page 131: ... by the capture event Each timer or timer half can be independently clocked from one of 4 clock sources Clock source can be independently set for each half of the timer in split mode The clock sources available for each timer half are 1 Current system clock clk_sys This is 24MHz possibly divided by N th power of 2 with N 0 7 See SYSGEN SFR register for system clock setting details 2 Current system...

Page 132: ...ode TMR2INTH set if capture event happens and TMR2H TMR2L 16 bit value gets captured TMR2INTL set if TMR2H overflows Note This is an exception when low interrupt flag gets set based on the high half of the timer This is a supplemental information for the interrupt handler about the capture indicating that the 16 bit counter overflew in between captures Split mode l Timer mode TMR2INTH set if TMR2H...

Page 133: ... capture event can be positive edge negative edge or both edges of the GPIO associated with the INT0 and INT1 Capture mode can be used for measurement of time inter vals on external signals Timer counts up and overflows from 0xFFFF to 0x0000 Each time a capture event is received the con tents of the timer registers TMR2H TMR2L are latched into the timer reload registers TMR2RH TMR2RL A timer high ...

Page 134: ... halves operate as two independent 8 bit timers with indepen dently set clocks As the 8 bit timer register increments and overflows from 0xFF to 0x00 the 8 bit value in the time reload registers TMR2RH or TMR2RL is loaded into the corresponding timer register TMR2H or TMR2L and the corresponding byte overflow flag TMR2INTH or TMR2INTL are set respectively If timer interrupts are enabled see IE and...

Page 135: ...mer reload registers TMR2RH and TMR2RL Common capture event INT0 INT1 for Timer 3 sets both high and low half interrupt flags TMR2INTH and TMR2INTL at the same time The capture event can also generate its own external interrupt on top of the timer interrupt if enabled by the application If the capture timer is stopped TMR2L_RUN 0 the capture event still captures the cur rent counter register TMR2L...

Page 136: ...hese two scenarios are the interrupt flags settings since TMR2INTH and TMR2INTL are not symmetrical The TMR2INTL has a local enable TMR2INTL_EN The functionality of the 8 bit timer and 8 bit capture modes for the respective halves is the same as described above when both halves operate in the same mode TMR3H_MODE TMR3L_MODE 0 1 TMR2H_RUN 2 3 clk_sys 12 rtc_tick 5 33us rtc_pulse 100us TMR2H_MODE TM...

Page 137: ..._MODE TMR3L_MODE 0 1 TMR2H_RUN 2 3 clk_sys 12 rtc_tick 5 33us rtc_pulse 100us TMR2H_MODE TMR2L_MODE 2 clk_sys TMR_CLKSEL 0 1 TMR2L_RUN 2 3 2 TMR2L TMR2RL TMR2H TMR2RH TMR2CTRL TMR2INTH TMR2INTL TMR2INTL_EN TMR2SPLIT TMR2H_CAP Interrupt TMR2L_CAP TMR2H_RUN TMR2L_RUN Capture INT0 INT1 for TMR3 Reload ...

Page 138: ..._MODE TMR3L_MODE 0 1 TMR2H_RUN 2 3 clk_sys 12 rtc_tick 5 33us rtc_pulse 100us TMR2H_MODE TMR2L_MODE 2 clk_sys TMR_CLKSEL 0 1 TMR2L_RUN 2 3 2 TMR2L TMR2H TMR2CTRL TMR2INTH TMR2INTL TMR2INTL_EN TMR2SPLIT TMR2H_CAP Interrupt TMR2L_CAP TMR2H_RUN TMR2L_RUN INT0 INT1 for TMR3 TMR2RH Capture TMR2RL Reload ...

Page 139: ...RTC_PULSE 100 µs 5 4 TMR3L_ MODE Timer 3 Low Byte Mode Select Timer 3 low half in split mode or full timer in wide mode clock selection 00 CLK_SYS 01 CLK_SYS 12 10 RTC_TICK 5 33 µs 11 RTC_PULSE 100 µs 3 2 TMR2H_ MODE Timer 2 High Byte Mode Select Timer 2 high half in split mode Ignored if Timer 2 is in wide mode 00 CLK_SYS 01 CLK_SYS 12 10 RTC_TICK 5 33 µs 11 RTC_PULSE 100 µs 1 0 TMR2L_ MODE Timer...

Page 140: ...e this bit is set when the high half of the timer overflows Since in that case the capture event is the same for both halves the capture event sets the TMR2INTH interrupt flag Then this TMR2INTL can be used as a flag that the timer overflew serving as an additional 17th timer bit in cap ture mode in wide configuration 5 TMR2 INTL_EN Timer 2 Low Byte Interrupt Enable When set to 1 this bit enables ...

Page 141: ...te Run Model TMR2H high byte enable in split configuration Ignored if timer operates in wide con figuration 0 TMR2L_ RUN Timer 2 Low Byte Run Model TMR2L low byte enable in split configuration whole timer enable in wide configura tion Bit Name Function ...

Page 142: ...wo halves are not double buffered Write to each of the halves takes effect immedi ately If the timer or respective half operates in capture mode this register holds the capture value If the timer or respective half operates in timer mode this register holds the reload value SFR Definition 34 4 TMR2RH Bit 7 6 5 4 3 2 1 0 Name TMR2RH 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 TMR2RH 7 ...

Page 143: ...mode the TMR2L register contains the low byte of the 16 bit Timer 2 In 8 bit mode TMR2L contains the 8 bit low byte timer value SFR Definition 34 6 TMR2H Bit 7 6 5 4 3 2 1 0 Name TMR2H 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 TMR2H 7 0 Timer 2 High Byte Actual Timer Value In 16 bit mode the TMR2H register contains the high byte of the 16 bit Timer 2 In 8 bit mode TMR2H contains the...

Page 144: ...it is set when the high half of the timer overflows Since in that case the capture event is the same for both halves the capture event sets the TMR3INTH interrupt flag Then this TMR3INTL can be used as a flag that the timer overflew serving as an additional 17th timer bit in cap ture mode in wide configuration 5 TMR3 INTL_EN Timer 3 Low Byte Interrupt Enable When set to 1 this bit enables Timer 3 ...

Page 145: ... Byte Run Model TMR3H high byte enable in split configuration whole timer enable in wide configura tion 0 TMR3L_ RUN Timer 3 Low Byte Run Model TMR3L low byte enable in split configuration whole timer enable in wide configura tion Bit Name Function ...

Page 146: ...wo halves are not double buffered Write to each of the halves takes effect immedi ately If the timer or respective half operates in capture mode this register holds the capture value If the timer or respective half operates in timer mode this register holds the reload value SFR Definition 34 9 TMR3RH Bit 7 6 5 4 3 2 1 0 Name TMR3RH 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 TMR3RH 7 ...

Page 147: ...mode the TMR3L register contains the low byte of the 16 bit Timer 3 In 8 bit mode TMR3L contains the 8 bit low byte timer value SFR Definition 34 11 TMR3H Bit 7 6 5 4 3 2 1 0 Name TMR3H 7 0 Type R W Reset 0 0 0 0 0 0 0 0 Bit Name Function 7 0 TMR3H 7 0 Timer 3 High Byte Actual Timer Value In 16 bit mode the TMR3H register contains the high byte of the 16 bit Timer 3 In 8 bit mode TMR3H contains th...

Page 148: ...formed when the device is in the halt state where all on chip peripherals and user software are stalled In this halted state the C2 interface can safely borrow the C2CLK GPIO 5 and C2DAT GPIO 4 pins In most applications external resistors are required to isolate C2 interface traffic from the user application A typical isolation configuration is shown in Figure 35 1 along with the connection to the...

Page 149: ...the current position where the code was halted If IDE is disconnected from the device the user application behaves exactly as programmed with the LED driver driving the LED per user application The user then can connect to the device through IDE by hitting the Connect button The connection is only possible when the LED driver is not active Upon connection the IDE will disable the LED driver for th...

Page 150: ...If pushbutton on keyfob development board then it has to be isolated by R5 For debugging chain to work LED must be isolated by R6 1k VBUS 5V Can be used to generate local VDD GPIO 4 Bidirectional for application use isolated from the C2 R2 ToolStick PCB edge connector 1 2 3 4 9 11 10 14 7 8 5 6 12 13 1k VDD VDO 3 3V 200mA Can be used directly as local VDD R4 1k R1 ...

Page 151: ...s are refreshed in RAM and regis ters If the part is a Factory part the previously loaded CODE XDATA RAM content is not disturbed If the part is a User part then the User data region is loaded as well overwriting the content of the CODE XDATA RAM Using IDE is the only way to reset the chip without cycling the power to it or shutting it down and waking it up 36 1 Functionality Limitations While Usi...

Page 152: ...turned on To share the LED and C2CLK functionality on a single pin and be able to use IDE for debugging there are some limitations and rules to follow Figure 35 1 and Figure 35 2 show the recommended connection of the debug adapters to the device in the user application Note that the LED must be isolated by the 470 resistor for the debugging chain to work If the debugging in the user application i...

Page 153: ...nd walk around with running application using LED as desired by the application The only thing the user has to do is to Disconnect the keyfob from the IDE by pressing the Disconnect button The LED gets enabled and the application runs from the point where the application is currently halted To run the application from the very beginning the user must press Reset on the IDE before pressing Disconne...

Page 154: ...Si401x Transmitters AN370 Si4010 Software Programming Guide AN511 Si4010 NVM Burner user s guide AN515 Si4010 Key fob Development Kit Quick Start Guide AN518 Si4010 Memory Overlay Technique AN526 Si4010 ROM 02 00 API Additional Library Description AN577 Si4010 NVM Read Reliability Analysis ...

Page 155: ... MHz Updated section 2 Ordering Information to reflect the revision B and C silicon Updated table 7 3 DC Characteristics to reflect revision B and C silicon Updated table 7 4 Si4010 RF Transmitter Characteristics to reflect revision B and C silicon Fixed block diagram in figure 8 1 Test Block Diagram with 10 pin MSOP Package Updated section 10 System Description text for revision B and C silicon U...

Page 156: ...licon Laboratories assumes no responsibility for the function ing of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of the application...

Page 157: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Silicon Laboratories Si4010 B1 GS Si4010 B1 GT SI4010 B1 GS SI4010 B1 GT ...

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