Siemens APACS+, Installation And Service Instruction

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SD39EAM-1r4 Circuit Description
September 2005 4-1
4 Circuit Description
The Enhanced Analog Module (EAM) is an APACS+ I/O module that is capable of communicating with
an APACS+ control module (ACM) by way of the IOBUS. Figure 4-1 is a simplified block diagram of
the signal processing portion of an EAM. Figure 4-2 is a block diagram of 1 of the 16 identical
input/output channels.
An EAM plugs in to a single MODULRAC or SIXRAC slot. The module’s bottom rear connector mates
with either the EAM Termination Strip for local I/O connections or the EAM Interconnect I/O Cable,
which in turn connects to an EAM Marshalled Termination Assembly, for remote I/O connections. A
Local Termination Panel is needed to mount an EAM Termination Strip when local termination is
employed. The Panel is not needed when marshalled (remote) terminations are installed.
The EAM consists of the following elements:
•
I/O Channel ASICs (Application Specific Integrated Circuits) - Process input/output signals.
•
CPU - Provides interfacing to the IOBUS and channel ASICs and control of I/O circuits.
•
Memory (RAM and EPROM) - Stores module executable code and configuration parameters.
•
IOBUS Modem - Provides digital data and command conversion needed for communication between
the EAM and control module.
•
I/O Communications Timing Circuit - Provides data/command and timing conversion needed for
communication between the CPU and 16 channel ASICs.
•
Redundancy circuit - Provides mode select/control/status signal conversion between the controller
and EAM.
•
Peripherals circuits - Provides data and command conversion needed for communication between the
CPU and the redundancy circuits, and channel Groups A and B optoisolators.
•
LED Indicators (on module bezel) - An “ACTIVE” LED indicates that the module is enabled. An
"OK" LED indicates the module status.
4.1 I/O Communications
Serial communication between Group A and B channel I/O ASICs and the CPU occurs via pulse
transformers coupled to two (A and B) half-duplex, bi-directional, synchronous party-line data buses.
The A and B party-line buses, each of which hosts 8 ASICs, are interfaced to serial multi-protocol ports
of the CPU via an I/O communications timing circuit consisting of isolation transformers, dual high-speed
line receivers and a programmable logic IC.
The communications format is a simplified HDLC (High-level Data Link Control) protocol. The clock
used for I/O communications is the same as the ASIC clock. The ASIC clock is derived from a channel’s
power transformer secondary waveform. A transformer is driven by a 368 KHz DC-to-DC converter.
Each channel ASIC produces an I/O value 180 times a second. Messages are sent to and from the ASIC
at a rate of 180 Hz. Part of the ASIC’s internal timing is based on receiving a poll message from the CPU
at precisely this rate. The I/O Communications Timing interface circuit ensures that messages between
the CPU and ASIC are correctly “paced” to accommodate 1440 transmit messages per second (8 ASICs
@ 180 Hz) per CPU multi-protocol port. Since each ASIC replies to its own message from the CPU,
there are also 1440 receive messages per second per CPU multi-protocol port.