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PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1.
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The Choice: Enabled or Disabled.
Memory Hole
You can reserve this area of system memory for ISA adapter ROM.
When this area is reserved, it can't be cached. The user information of
peripherals that need to use this area of system memory ususlly dis-
cusses their memory requirements.
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The Choice: Disabled or 15M-16M.
VLINK Data Rate
This item allows you to set VLINK Data Rate.
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The Choice: 8x or 4x.
Init Display First
This item allows you to decide to activate whether PCI slot or AGP first.
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The choice: PCI Slot or AGP/Onboard.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-
FFFFFh, resulting in better system performance. However, if any pro-
gram is written to this memory area, a system error may result.
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The choice: Enabled or Disabled.
