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LDT & PCI Bus Control
Options are in its sub-menu.
Press <Enter> to enter the sub-menu of detailed options.
Upstream LDT Bus Width
This item allows you to select the LDT upstream width.
Ø
The Choice: 8 bit or 16 bit.
Downstream LDT Bus Width
This item allows you to select the LDT downstream width.
Ø
The Choice: 8 bit or 16 bit.
LDT Bus Frequency
The item selects the LDT bus frequency.
Ø
The Choice: Atuo, 200 MHz, 400 MHz, 600 MHz or 800 MHz.
PCI1 Master 0 WS Write
When this item enabled, writing to the PCI bus is executed with zero
wait state.
Ø
The Choice: Enabled or Disabled.
PCI2 Master 0 WS Write
When this item enabled, writing to the AGP bus is executed with zero
wait state.
Ø
The Choice: Enabled or Disabled.
PCI1 Post Write
This Item enable/disable AGP post write function, which means when
cpu accessing the AGP data, the chipset can queue the instruction
when the AGP bus is busy, then write the data when AGP bus is avail-
able .
Ø
The Choice: Enabled or Disabled.
PCI2 Post Write
This Item enable/disable PCI post write function, which means when
cpu accessing the PCI data, the chipset can queue the instruction when
the PCI bus is busy, then write the data when AGP bus is available.
Ø
The Choice: Enabled or Disabled.
