Section 6 SMT-200 Technical
Io
SENSOR
78
SMT-200 Operations and Technical Manual 2.00/R1
6.10 Filter
The filter circuit is shown on sheet 3. of the SMT-200 Schematic.
Once the analogue signal has left the D to A converter it passes through a buffer (U8A) and to a high
pass filter. After this it passes directly to an attenuator. The amount of attenuation is set by the data
word set on D0 to D7. From here the signal passes to the geophone circuit.
6.11 Geophone
Circuit
The geophone circuit is shown on sheet 6. of the SMT-200 Schematic.
The signal from the filter is buffered (U17B) and passed to an amplifier circuit. The geophone under
test is in the feedback path of the amplifier, so the output of the circuit is dependant on the geophone.
As a reference a high precision, 499 W resistor can be substituted for the geophone. This is selected
by the O2 (pin 22) of the PPI. O2 switches relay K1 via the mosfet Q3. Using a method of comparison
with the reference resistor (R30) the effects of temperature drifts and offsets can be minimised.
The output of the driven geophone is fed to a programmable gain amplifier based on U17C and U16.
The feedback resistor of the amplifier is selected by the code on O3 to O5. U16 is a programmable
switch that will select R19 to R26.
The output of the programmable amplifier is fed to a selector, U18. This device has two 4 to 1
encoders whose outputs are selected by the code on the A0 (pin 16) and A1 (pin 1). The control signal
for these originate on O6 and O7 of the PPI.
A1 A0
1-4 5-8
0 0
Geophone
Not
used
0
1
Leakage
x 100 or Battery monitor option
1 0 Leakage
x
1000
1 1 Leakage
x
10000
In the case of geophone data the data passes straight through the selector. If leakage is selected the
gain applied is dependant on the code on A0 and A1.
The leakage circuit works applying a DC signal to the geophone and amplifying any signal picked up
on the leakage terminal (LEAK). The signal that appears on the LEAK terminal is assumed to have
originated from the geophone and only appears due to leakage of the string. Two (or three) gain
settings are selected automatically as shown in the above table. (see also page 32)
6.12
Analogue to Digital Converter
The A to D circuit is shown on sheet 2. of the SMT-200 Schematic.
The A to D is based on U6. This is a CMOS based 16-Bit sampling A to D converter using a
successive approximation technique. This chip has the advantage of having a built in sample and hold
circuit and can digitise a signal within 25
µ
S.
The signal to be digitised appears on the R1IN pin via R2. The conversion process is started by the
R/-C input being forced low. Shortly after this -BUSY will go low to indicate that a conversion is in
process. The CPU can monitor this via PA0 of the 8255 PPI. Once conversion has been completed
