Io
SENSOR
Section 6 SMT-200 Technical
SMT-200 Operations and Technical Manual 2.00/R1
77
6.8 Keyboard
The keyboard circuit is shown on sheet 7 of the SMT-200 Schematic.
The keyboard is a 4 x 4 membrane keypad with an additional switch for the ENTER/START key. This
feeds a 16 key encoder IC based on U9. This IC will scan the keyboard matrix at a rate determined by
the capacitor on pin 5. When a key is pressed the key is debounced (the debounce period is set by
value C10 on pin 6) and the DAV line (pin 12) is asserted. This is polled and read on I4, pin 44 of the
PPI. The data on pins 14 to 16 at this stage is stable and can be read directly by the PC. The data is a
4 bit code that represents the key pressed.
The
ENTER/START
key is active low and does not go through the encoder but is fed directly to the PPI.
6.9
Digital to Analogue Converter
The digital to analogue converter circuit is shown on sheet 7 of the SMT-200 Schematic.
The digital to analogue converter (DAC) is formed around a lookup table stored in the EPROM, U12.
This contains the digital values for a low distortion sine wave. The clock for each sample starts at the
PC speaker. The PC speaker frequency can be altered by the software. The output that would
normally be fed to the speaker is firstly buffered by Q2 and sent to an address generator (U10) and a
selector (U15). The address generator is a 12 stage binary counter clocked by Q2. The incrementing
address is fed to the EPROM that generates the data samples. This is then fed to the DAC which
converts the sample to an analogue signal.
The selector U15, selects the function of the PC speaker. It has a three functions :
•
Address Generator Clock
•
A to D Converter convert signal
•
Audio Speaker
The signal that appears on 1Y of U15 is selected from one of the inputs on 1C0, 1C1, 1C2 and 1C3
and similarly the signal on 2Y is selected form 2C0, 2C1, 2C2 or 2C3. The particular output is set by
the 2 digit code on lines A and B of U15.
B (O1)
A(O0)
1Y (CONVERT) 2Y (SP+ SP-)
0
0
Note 1
0 v
0 1 PC-SP 0
v
1 0 VCC PC-SP
1 1 0
v PC-SP
Note 1
Pulsed low every 32
clock cycles of PC-SP
