Samsung SC-D263, Service Manual

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Reference Information
Samsung Electronics 14-33
4) FIFO
Core has an Endpoint 0 FIFO that handles the standard descriptor and the class specific descriptor.
And that FIFO is connected to a microcontroller decode block.
The user can define the size of FIFO.
Except EPO FIFO, only FIFOs that have configurable direction control can support the unidirectional operation
through a certain configuration. The maximum packet size for the In and Out tokens are set up through the
register. All In/Out FIFOs are connected to the microcontroller decode block.
5) Microcontroller Decode Block
This block is composed of the internal register decoding block and the microcontroller interface block.
This microcontroller interface has addresses and data bus interfaces that are either synchronous or
asynchronous.
This core improves the performance by reducing the microcontroller's burden via a data buffering.
6) Internet Register
Using of the indexing scheme by the internal register for the endpoint register is as follows:
- IN_CSR (IN Control Status Register)
- OUT_CSR (OUT Control Status Register)
- IN_MAXP (IN Maximum Packet Size Register)
- OUT WRITE COUNT
If the core does not include any OUT endpoint, OUT_CSR does not exist. However, OUT WRITE COUNT
register exists to read WRITE, the count for the endpoint 0.
Interrupt (Status) and Interrupt Enable register are divided into two banks.
- Endpoint Interrupts
- USB Interrupts
If there is no endpoint that is larger than endpoint #8, ENDPOINT INTERRUP2 register and ENDPOINT
INTERRUPT ENABLE register do not exist.
MAXP, ENDPOINT INTERRUPT, END POINT INTERRUPT ENABLE registers are used regardless of the
direction of endpoints. For example, if an endpoint that has an OUT direction is chosen by the INDEX register,
ENDPOINT INTERRUPT register would provide an endpoint along with the OUT interrupt information.
On the other hand, the CSR register that is connected for each endpoint must be indexed, and can be different
according the certain endpoint direction.