3.2 : VPX Connectors
This section details the signals on the VPX connectors as implemented on the VP3500.
3.2.1 : VPX P0
VITA 46 defines VPX connector P0 as part of the VPX Utility plane. This plane is used to supply the add-
in card’s voltages, clocks, board-to-board communication, geographical addressing, and system reset.
Pin
Row G
Row F
Row E
Row D
Row C
Row B
Row A
1
+12V
+12V
+12V
NC
+12V
+12V
+12V
2
+12V
+12V
+12V
NC
+12V
+12V
+12V
3
+5V
+5V
+5V
NC
+5V
+5V
+5V
4
IPMBB_CLK IPMBB_DAT
GND
AUX_-12V
GND
VRESET_L
NVMRO
5
GAP_L
GA4_L
GND
AUX_3_3V
GND
IPMBA_CLK IPMBA_DAT
6
GA3_L
GA2_L
GND
AUX_+12V
GND
GA1_L
GA0_L
7
NC
GND
NC
NC
GND
NC
NC
8
GND
NC
NC
GND
CLK_AUX-
GND
Table 2 : VPX P0 Signals
IPMBx_CLK/DAT
These signals are reserved for System Management functions such as IPMI and board-to-board
communications. These may be defined in protocol specifications or by specific system requirements.
The VP3500 makes use of these signals for system controller communications with the VP3500’s
microcontroller. The microcontroller responds to commands issued by the host controller or, potentially,
other boards in the system. These signals are open collector I2C signal levels. Please see section 5.3 for
supported commands.
GAx_L
These low-true input pins are defined for system-wide geographical addressing. They are pulled up
on the VP3500 to +3.3V and are routed to the microcontroller. The microcontroller uses these signals to
determine the slot the card is plugged into and defines it IPMI (I2C) addressing.
VP3500 User Manual • Document Number 101-3500-0001 • Revision A0
Property of Rigel Engineering, LLC. Confidential & Proprietary
690 Cone Park Court, Merritt Island, Florida 32952
page 29