Rigel VP3500 User Manual Download Page 44

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These are the differential reference clock pair for the XMC 2 PCI Express interface. This differential

signal pair is generated by the VP3500 and transmitted to the mezzanine. This signal is required to be

provided for PCI Express add-in boards and is used to synchronize devices on both ends of a link. This

clock is 100MHz (+/- 300ppm) however please refer to the PCI Express Electromechanical Specification

for the detailed requirements of this signal.

An XMC may use CLK-REF to derive its on board PCI Express interface clocks although it is not

required.

TRST_L, TCK, TMS, TDI & TDO

XMC JTAG signals. XMC JTAG chain testing is not supported on the VP3500. TRST_L is connected to

ground, TCK, TMS & TDI are pulled up to +3.3V through 8.2K ohm resistors and TDO is not connected.

MBIST_L

XMC Built In Self Test. This signal allows the VP3500 to determine whether an XMC has completed its

built-in self test. If this signal is used, it shall be asserted low at the de-assertion of RESET_L to indicate

that the XMC is performing self-test and is not yet ready. This VP3500 input signal is pulled up to +3.3V

through an 8.2K ohm resistor and routed to microcontroller pin 54.

GA[2:0]

XMC I2C Geographical Address. These signals allow the VP3500 to address a specific XMC slot. The

XMC decodes these signals to determine its IPMI I2C address as shown in VITA specification 42.0, Table

5-2. The GA address for XMC slot 2 is 001.

NVMRO

Non Volatile Memory Read Only or XMC Write Prohibit. When this signal is asserted high, the XMC

shall disable writes to non-volatile memory on the XMC. This signal is an input to the XMC card and is

generated by a device on the VPX backplane.

WAKE_L

An open-drain, active low signal that is driven low by an XMC PCI Express function to reactivate the

links main power rails and reference clocks. The VP3500 does not support XMC power on/off control,

therefore, the WAKE function is routed to both XMCs and pulled up to +3.3V through an 8.2K resistor.

VP3500 User Manual • Document Number 101-3500-0001 • Revision A0

Property of Rigel Engineering, LLC. Confidential & Proprietary

690 Cone Park Court, Merritt Island, Florida 32952

page 44

Summary of Contents for VP3500

Page 1: ...land Florida 32952 Engineering LLC Model VP3500 User Manual 6U VPX Dual PMC XMC MiniPCIe Carrier card with Integrated 5 Port Gigabit Ethernet Switch page 1 Revision A0 October 9 2013 Document Number 101 3500 0001 Property of Rigel Engineering LLC Confidential Proprietary 690 Cone Park Court Merritt Island Florida 32952 Information subject to change ...

Page 2: ...nizes the following trademarks and their respective owners for components used on the VP3500 and references made in this document VITA VPX VPX REDI OpenVPX XMC and XMC logos are trademarks of VITA PCI Express and logo are trademarks of PCI SIG Rigel Engineering LLC recognizes all trademarks products and companies that may be mentioned in this document Copyright Copyright 2013 Rigel Engineering LLC...

Page 3: ...d Heat Frame 18 Section 2 Configuration and Installation 2 1 Overview 19 2 2 Unpacking 19 2 3 Card Identification 19 2 4 PMC XMC MiniPCIe Installation Removal 19 2 4 1 Air Cooled PMC Installation and Removal 21 2 4 2 Conduction Cooled PMC Installation and Removal 22 2 4 3 Air cooled XMC Installation and Removal 23 2 4 4 Conduction Cooled XMC Installation and Removal 24 2 4 5 MiniPCIe Installation ...

Page 4: ... connector 71 Section 4 VP3500 Specifications 4 1 Physical Specifications 76 4 2 Environmental Specifications 76 4 3 Electrical specifications 77 4 4 PCIe Switch Specifications 77 4 5 MiniPCIe Specifications 78 4 6 PMC Specifications 78 4 7 VPX Fabric Specifications 78 4 8 XMC Specifications 79 4 9 Ethernet Specifications 79 Section 5 Operation 5 1 LEDs Indicators 80 5 1 1 Power OK LED 81 5 1 2 Gb...

Page 5: ...nds 89 5 3 3 1 Read Power Status 90 5 3 3 2 Read Board Serial Number 91 5 3 3 3 PEX8648 PCIe Switch Port 0 9 Status 91 5 3 3 4 EEPROM Read Write 92 5 3 3 5 Read Temperature 92 5 3 3 6 Set High Low Alert Temperature Limits 92 5 3 3 7 PMC XMC Status 93 5 3 3 8 MiniPCIe Wireless Enable Disable 93 5 3 3 9 MiniPCIe Wireless Status 93 5 3 3 10 Clear 94 5 3 3 11 I2C Bus Select 1 4 94 5 3 3 12 I2C Slave A...

Page 6: ...C 1 J12 Connector pin out 54 Table 19 PMC 1 J13 Connector pin out 55 Table 20 PMC 1 J14 Connector pin out 56 Table 21 PMC 2 J21 Connector pin out 57 Table 22 PMC 2 J22 Connector pin out 58 Table 23 PMC 2 J23 Connector pin out 59 Table 24 PMC 2 J24 Connector pin out 60 Table 25 PMC 1 IO Module connector 1 pin mapping 62 Table 26 PMC 1 IO Module connector 2 pin mapping 63 Table 27 PMC 2 IO Module co...

Page 7: ...ons 79 Table 42 GbE LEDs 81 Table 43 PCIe LEDs 82 Table 44 PCIe LED Pattern 82 Table 45 RT3500 Connector VP3500 HDR3 Serial Pins 84 Table 46 Microcontroller Serial Port Commands 85 Table 47 Microcontroller VPX Commands 90 Table 48 Power Status 90 Table 49 PCIe Switch Port Status 91 Table 50 PMC XMC Status 93 Table 51 MinePCIe Wireless Status 93 VP3500 User Manual Document Number 101 3500 0001 Revi...

Page 8: ...3500 61 Figure 10 MiniPCIe Sockets 66 Figure 11 MiniPCIe IO Module Locations 71 Figure 12 VP3500 LEDs Front Panel View 80 Figure 13 VP3500 PCIe Switch Default Configuration 83 Figure 14 RT3500 Microcontroller Serial Connector 84 Figure 15 VP3500 Microcontroller Serial Connector HDR3 84 Figure 16 VP3500 I2C Topology 96 VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Property of Rigel En...

Page 9: ...PCIe or PCI Express Peripheral Component Interconnect Express A high speed serial computer expansion bus standard designed to replace the older PCI PCI X and AGP bus standards PCI X Peripheral Component Interconnect Extended is a performance enhanced version of the PCI bus PMC A PCI Mezzanine Card is a printed circuit board manufactured to the IEEE P1386 1 standard This standard combines the elect...

Page 10: ... 64 bit performance PMC and XMC rear IO routing is configurable and adheres to VITA 46 9 P64s to VPX P3 P5 or X38s to P3 P5 X12d X8d to P4 P6 A pluggable IO module allows the system designer to mix and match the PMC or XMC selection and their IO requirements to the backplane Additionally the two MiniPCIe sockets support Full Mini or Half Mini card form factors with front panel and rear IO routing ...

Page 11: ...e following is a list of related documentation that may be helpful Please note that the documents listed are not controlled by Rigel Engineering LLC and may change without notice VITA 46 0 VPX Base Standard VITA 46 4 PCI Express on VPX Fabric Connector VITA 46 6 Gigabit Ethernet Control Plane on VPX Draft Revision 0 7 July 19 2010 VITA 46 9 PMC XMC Rear IO Fabric Signal Mapping 3U and 6U VPX Modul...

Page 12: ... J11 J21 J23 J22 J24 J15 J16 J25 J26 PCIe to PCI X Bridge PCIe to PCI X Bridge PCIe Switch Full mini PCIe card MiniPCIe RIO Full mini PCIe card GbE Switch Magnetics Mini PCIe RIO Magnetics To P6 GbE Figure 2 VP3500 Block Diagram VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Property of Rigel Engineering LLC Confidential Proprietary 690 Cone Park Court Merritt Island Florida 32952 pag...

Page 13: ...nal bus speeds of 33 and 66MHz and PCI X speeds of 66 and 133MHz The PMC slots conform to ANSI VITA 20 2001 standard for conduction cooled PMC devices The conduction cooled heat frame design allows for optional front panel PMC IO Standard and conduction cooled PMC modules may be used which adds to the VP3500 s flexibility The PMC rear IO routing conforms to VITA specification 46 9 P64S to VPX P3 P...

Page 14: ... or conduction cooled frame will not likely work since all MiniPCIe cards are different The VP3500 heat frames are designed with a removable section for the MiniPCIe cards This allows a specific heat frame solution for each set of MiniPCIe cards 1 4 5 Integrated 5 Port GbE Switch The VP3500 includes an integrated 5 port Gigabit Ethernet switch The switch is configured to VPX standard Vita 46 6 rou...

Page 15: ...e please refer to the data sheet that can be downloaded from www onsemi com 1 5 Options and Accessories 1 5 1 Overview TheVP3500isdesignedforapplicationsthatincludecommercialtemperature air cooledtoextendedtemperature and conduction cooled for more rugged environments Astandard air cooled VP3500 provides access for the PMC XMC and MiniPCIe front panel IO while the conduction cooled models provide ...

Page 16: ...offers custom designed IO modules for customer specific routing requirements Please contact Rigel Engineering for ordering and additional information on obtaining custom IO modules The standard IO modules offered are for PMC and XMC VITA46 9 applications Figure 3 Picture of IO Module Standard IO Module Ordering Information For XMC applications please order the IM3500 0000 For PMC applications plea...

Page 17: ...le Rigel Engineering offers a rear transition IO module with industry standard connectors for the board s backplane IO access Rigel Engineering will also provide a quick turn custom rear transition IO module for your requirements The standard rear transition module RT3500 0000 provides access to the following IO VP3500 Momentary reset switch VP3500 Momentary power up down switch Microcontroller em...

Page 18: ...P1 JT1 HDR3 J10 GbE P4 GbE P5 J3 J4 Power Switch J11 HDR1 HDR2 Serial Port Figure 4 RT3500 0000 VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Property of Rigel Engineering LLC Confidential Proprietary 690 Cone Park Court Merritt Island Florida 32952 page 18 ...

Page 19: ...stalled for the MiniPCIe cards If you have a special request for more options on the heat frame please contact Rigel Engineering support Ordering Information VP3500 xx00 Base Model Operating Temperature Cooling Options 0 0 C to 70 C Air Cooled 1 40 C to 85 C Air Cooled 2 40 C to 85 C Conduction Cooled 3 40 C to 85 C Conduction Cooled REDI 0 85 Z Customer specific board configuration MiniPCIe Conne...

Page 20: ... packing slip have been received in good condition 2 3 Card Identification There are no jumpers that need to be configured on the VP3500 However there are four header locations that provide access to various signals and functionality Some or all of these headers are not populated are only used for lab testing or may be accessed on the rear transition module Figure 6 identifies the card s features ...

Page 21: ...A0 Property of Rigel Engineering LLC Confidential Proprietary 690 Cone Park Court Merritt Island Florida 32952 page 21 Microcontroller Serial Header MiniPCIe 1 PMC XMC 1 IO Mod IO Mod PMC XMC 2 M P 1 I O M P 2 I O MiniPCIe 2 MiniPCIe 1 Rear IO Adapter Connector MiniPCIe 2 Rear IO Adapter Connector ...

Page 22: ...nto the VP3500 front panel PMC opening 7 Align the PMC connectors on the module with the connectors on the VP3500 and carefully but firmly press down until the connectors make a clean and solid connection 8 Turn the VP3500 over and insert the four mounting screws that are provided with the PMC through the holes on the bottom side of the VP3500 into the PMC front bezel and rear standoffs Tighten th...

Page 23: ...e PMC module faceplate side into the VP3500 front panel PMC opening 6 Align the PMC connectors on the module with the connectors on the VP3500 and carefully but firmly press down until the connectors make a clean and solid connection 7 Install the PMC mounting screws that are provided with the PMC card to the heat frame on the top side of the VP3500 Tighten the screws Rugged applications should us...

Page 24: ...he VP3500 front panel XMC opening 7 Align the XMC connectors on the module with the connectors on the VP3500 and carefully but firmly press down until the connectors make a clean and solid connection 8 Turn the VP3500 over and insert the four mounting screws that are provided with the XMC through the holes on the bottom side of the VP3500 into the XMC front bezel and rear standoffs Tighten the scr...

Page 25: ...r on the threads 8 Reinstall the VP3500 into the VPX backplane from the slot from which it was removed 9 Replace the system AC power cord and power up the system For removal of the XMC follow the above mechanical steps in reverse 2 4 5 MiniPCIe Installation and Removal To install a MiniPCIe module proceed with the following steps 1 Attach an ESD wrist strap to your wrist and securely attach the ot...

Page 26: ...t the AC plug from the system 4 Carefully remove the VP3500 from the VPX chassis and place it on a cushioned flat surface An ESD pad is the ideal option 5 Carefully align the IO module s connectors to the connectors on the VP3500 and press down firmly 6 Install the IO module s mounting screws to the heat frame on the top side of the VP3500 Tighten the screws Rugged applications should use Loctite ...

Page 27: ...ely attach the other end to chassis ground 2 Turn the system power off and remove the AC power cord 3 Follow previous steps to install PMC XMCs and MiniPCIe cards 4 Carefully slide the VP3500 into a VPX payload slot Take caution to seat the card firmly in the chassis by using the ejector handles If you are using a conduction cooled model tighten the wedge locks 5 Attach and secure all cables if us...

Page 28: ...ors on the VP3500 Figure 7 VP3500 Connectors P0 P1 P2 P3 P4 P5 P6 J15 J16 J25 J26 J11 J12 J13 J14 J21 J22 J23 J24 MPCIe 1 MPCIe 2 MP1 IO MP2 IO VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Property of Rigel Engineering LLC Confidential Proprietary 690 Cone Park Court Merritt Island Florida 32952 page 28 ...

Page 29: ...anagement functions such as IPMI and board to board communications These may be defined in protocol specifications or by specific system requirements The VP3500 makes use of these signals for system controller communications with the VP3500 s microcontroller The microcontroller responds to commands issued by the host controller or potentially other boards in the system These signals are open colle...

Page 30: ...ed to the NVMRO pins on each XMC connector and the on board EEPROM write protect pin CLK_AUX These 1 PPS differential input signals to the VP3500 are translated to LVTTL levels then routed to each XMC PMC IO module This reference timing source is defined with relatively tight accuracy and stability specifications and is driven differentially on the backplane in order to provide high signal integri...

Page 31: ... GND DP3_ T1 DP3_ T1 GND DP3_ R1 DP3_ R1 GND 11 RTM_UD2 GND DP3_ T2 DP3_ T2 GND DP3_ R2 DP3_ R2 12 GND DP3_ T3 DP3_ T3 GND DP3_ R3 DP3_ R3 GND 13 RTM_UD3 GND DP4_ T0 DP4_ T0 GND DP4_ R0 DP4_ R0 14 GND DP4_ T1 DP4_ T1 GND DP4_ R1 DP4_ R1 GND 15 MRESET_L GND DP4_ T2 DP4_ T2 GND DP4_ R2 DP4_ R2 16 GND DP4_ T3 DP4_ T3 GND DP4_ R3 DP4_ R3 GND Table 3 VPX P1 Signals P1_G1 Not used but is pulled up to AU...

Page 32: ...lt configuration for the data plane is a 4x4 but may be configured as 1x16 or 2x8 as well The ports will also auto negotiate to fewer lanes if the full port width is not supported See section 5 3 for configuration options DP1 The 4 lane PCIe Port FAT Pipe connected to PCIe switch port 4 in 4x4 configuration DP2 The 4 lane PCIe Port FAT Pipe connected to PCIe switch port 5 in 4x4 configuration DP3 ...

Page 33: ...D MP1_DX10 MP1_DX10 GND 7 MP1_SE3 GND MP1_DX13 MP1_DX13 GND MP1_DX12 MP1_DX12 8 GND MP1_DX15 MP1_DX15 GND MP1_DX14 MP1_DX14 GND 9 MP2_SE0 GND MP2_DX1 MP2_DX1 GND MP2_DX0 MP2_DX0 10 GND MP2_DX3 MP2_DX3 GND MP2_DX2 MP2_DX2 GND 11 MP2_SE1 GND MP2_DX5 MP2_DX5 GND MP2_DX4 MP2_DX4 12 GND MP2_DX7 MP2_DX7 GND MP2_DX6 MP2_DX6 GND 13 MP2_SE2 GND MP2_DX9 MP2_DX9 GND MP2_DX8 MP2_DX8 14 GND MP2_DX11 MP2_DX11 G...

Page 34: ...2 PXMC1_14 GND 7 NC GND PXMC1_15 PXMC1_17 GND PXMC1_16 PXMC1_18 8 GND PXMC1_19 PXMC1_21 GND PXMC1_20 PXMC1_22 GND 9 RS232_TX GND PXMC1_23 PXMC1_25 GND PXMC1_24 PXMC1_26 10 GND PXMC1_27 PXMC1_29 GND PXMC1_28 PXMC1_30 GND 11 RS232_RX GND PXMC1_31 PXMC1_33 GND PXMC1_32 PXMC1_34 12 GND PXMC1_35 PXMC1_37 GND PXMC1_36 PXMC1_38 GND 13 PLT_RST_L GND PMC1_49 PMC1_51 GND PMC1_50 PMC1_52 14 GND PMC1_53 PMC1_...

Page 35: ...X RS 232 level Transmit data pin from the microcontroller serial data out pin 33 RS232_RX RS 232 level Receive data pin to the microcontroller serial data in pin 34 PLT_RST_L VP3500 Platform reset output signal This is an open collector type output to a rear transition module RTM UC_BKGD The Microcontroller background signal to the programming debug header on the RTM VP3500 User Manual Document Nu...

Page 36: ...XN P4_TXP GND P4_RXN P4_RXP GND 13 NC GND LP1_DB_M LP1_DB_P GND LP1_DA_M LP1_DA_P 14 GND LP1_DD_M LP1_DD_P GND LP1_DC_M LP1_DC_P GND 15 NC GND LP0_DB_M LP0_DB_P GND LP0_DA_M LP0_DA_P 16 GND LP0_DD_M LP0_DD_P GND LP0_DC_M LP0_DC_P GND Table 6 VPX P4 Signals XMC_1 VITA 46 9 X12d X8d differential IO direct routing from XMC 1 J16 to VPX P4 BLUE VITA 46 6 Gigabit Ethernet Control Plane on VPX P4 routin...

Page 37: ...D PXMC2_12 PXMC2_14 GND 7 NC GND PXMC2_15 PXMC2_17 GND PXMC2_16 PXMC2_18 8 GND PXMC2_19 PXMC2_21 GND PXMC2_20 PXMC2_22 GND 9 NC GND PXMC2_23 PXMC2_25 GND PXMC2_24 PXMC2_26 10 GND PXMC2_27 PXMC2_29 GND PXMC2_28 PXMC2_30 GND 11 NC GND PXMC2_31 PXMC2_33 GND PXMC2_32 PXMC2_34 12 GND PXMC2_35 PXMC2_37 GND PXMC2_36 PXMC2_38 GND 13 NC GND PMC2_49 PMC2_51 GND PMC2_50 PMC2_52 14 GND PMC2_53 PMC2_55 GND PMC...

Page 38: ...A11 XMC_2_B11 GND XMC_2_D11 XMC_2_E11 10 GND XMC_2_A13 XMC_2_B13 GND XMC_2_D13 XMC_2_E13 GND 11 MP2_SE5 GND MP1_DX17 MP1_DX17 GND MP1_DX16 MP1_DX16 12 GND MP1_DX19 MP1_DX19 GND MP1_DX18 MP1_DX18 GND 13 MP2_SE6 GND MP2_DX17 MP2_DX17 GND MP2_DX16 MP2_DX16 14 GND MP2_DX19 MP2_DX19 GND MP2_DX18 MP2_DX18 GND 15 MP2_SE7 GND LP2_DB_M LP2_DB_P GND LP2_DA_M LP2_DA_P 16 GND LP2_DD_M LP2_DD_P GND LP2_DC_M LP...

Page 39: ...GND MRSTO_L 5 DP1_T4 DP1_T4 3_3V DP1_T5 DP1_T5 VPWR 6 GND GND TMS GND GND 12V_AUX 7 DP1_T6 DP1_T6 3_3V DP1_T7 DP1_T7 VPWR 8 GND GND TDI GND GND 12V_AUX 9 NC NC NC NC NC VPWR 10 GND GND TDO GND GND GA0 11 DP1_R0 DP1_R0 MBIST_L DP1_R1 DP1_R1 VPWR 12 GND GND GA1 GND GND PRSNT_L 13 DP1_R2 DP1_R2 3_3V_AUX DP1_R3 DP1_R3 VPWR 14 GND GND GA2 GND GND I2C_DAT 15 DP1_R4 DP1_R4 NC DP1_R5 DP1_R5 VPWR 16 GND GN...

Page 40: ... of RESET_L to indicate that the XMC is performing self test and is not yet ready This VP3500 input signal is pulled up to 3 3V through an 8 2K ohm resistor and routed to microcontroller pin 53 GA 2 0 XMC I2C Geographical Address These signals allow the VP3500 to address a specific XMC slot The XMC decodes these signals to determine its IPMI I2C address as shown in VITA specification 42 0 Table 5 ...

Page 41: ...ecific reset Please refer to section 5 3 PRSNT_L XMC 1 Board Present This VP3500 low true input signal is routed to microcontroller pin 17 and is used to determine if an XMC card is plugged in or not The signal is pulled up to 3 3V through an 8 2K ohm resistor I2C_CLK DAT These two open drain signals provide the system management bus to the XMCs among other devices on the VP3500 Please refer to se...

Page 42: ...MC_1_F12 13 XMC_1_A13 XMC_1_B13 XMC_1_C13 XMC_1_D13 XMC_1_E13 XMC_1_F13 14 GND GND XMC_1_C14 GND GND XMC_1_F14 15 XMC_1_A15 XMC_1_B15 XMC_1_C15 XMC_1_D15 XMC_1_E15 XMC_1_F15 16 GND GND XMC_1_C16 GND GND XMC_1_F16 17 XMC_1_A17 XMC_1_B17 XMC_1_C17 XMC_1_D17 XMC_1_E17 XMC_1_F17 18 GND GND XMC_1_C18 GND GND XMC_1_F18 19 XMC_1_A19 XMC_1_B19 XMC_1_C19 XMC_1_D19 XMC_1_E19 XMC_1_F19 Table 10 XMC 1 J16 Sig...

Page 43: ...T5 DP1_T5 VPWR 6 GND GND TMS GND GND 12V_AUX 7 DP1_T6 DP1_T6 3_3V DP1_T7 DP1_T7 VPWR 8 GND GND TDI GND GND 12V_AUX 9 NC NC NC NC NC VPWR 10 GND GND TDO GND GND GA0 11 DP1_R0 DP1_R0 MBIST_L DP1_R1 DP1_R1 VPWR 12 GND GND GA1 GND GND PRSNT_L 13 DP1_R2 DP1_R2 3_3V_AUX DP1_R3 DP1_R3 VPWR 14 GND GND GA2 GND GND I2C_DAT 15 DP1_R4 DP1_R4 NC DP1_R5 DP1_R5 VPWR 16 GND GND NVMRO GND GND I2C_CLK 17 DP1_R6 DP1...

Page 44: ... of RESET_L to indicate that the XMC is performing self test and is not yet ready This VP3500 input signal is pulled up to 3 3V through an 8 2K ohm resistor and routed to microcontroller pin 54 GA 2 0 XMC I2C Geographical Address These signals allow the VP3500 to address a specific XMC slot The XMC decodes these signals to determine its IPMI I2C address as shown in VITA specification 42 0 Table 5 ...

Page 45: ...ecific reset Please refer to section 5 3 PRSNT_L XMC 2 Board Present This VP3500 low true input signal is routed to microcontroller pin 39 and is used to determine if an XMC card is plugged in or not The signal is pulled up to 3 3V through an 8 2K ohm resistor I2C_CLK DAT These two open drain signals provide the system management bus to the XMCs among other devices on the VP3500 Please refer to se...

Page 46: ...MC_2_F12 13 XMC_2_A13 XMC_2_B13 XMC_2_C13 XMC_2_D13 XMC_2_E13 XMC_2_F13 14 GND GND XMC_2_C14 GND GND XMC_2_F14 15 XMC_2_A15 XMC_2_B15 XMC_2_C15 XMC_2_D15 XMC_2_E15 XMC_2_F15 16 GND GND XMC_2_C16 GND GND XMC_2_F16 17 XMC_2_A17 XMC_2_B17 XMC_2_C17 XMC_2_D17 XMC_2_E17 XMC_2_F17 18 GND GND XMC_2_C18 GND GND XMC_2_F18 19 XMC_2_A19 XMC_2_B19 XMC_2_C19 XMC_2_D19 XMC_2_E19 XMC_2_F19 Table 12 XMC 2 J26 Sig...

Page 47: ... 14 15 XMC_1_C7 XMC_1_F8 16 17 XMC_1_C8 XMC_1_F9 18 19 XMC_1_C9 XMC_1_F10 20 21 XMC_1_C10 XMC_1_F11 22 23 XMC_1_C11 XMC_1_F12 24 25 XMC_1_C12 XMC_1_F13 26 27 XMC_1_C13 XMC_1_F14 28 29 XMC_1_C14 XMC_1_F15 30 31 XMC_1_C15 XMC_1_F16 32 33 XMC_1_C16 XMC_1_F17 34 35 XMC_1_C17 XMC_1_F18 36 37 XMC_1_C18 XMC_1_F19 38 39 XMC_1_C19 PXMC_1_ID_0 40 41 PXMC_1_ID_1 XMC_1_C1 To VPX P3 B3 42 43 NC XMC_1_F1 To VPX...

Page 48: ...hese two pins are module identification pins These signals may be read by the microcontroller The XMC X38s module IM3500 0000 ID pins are read as 00 respectively VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Property of Rigel Engineering LLC Confidential Proprietary 690 Cone Park Court Merritt Island Florida 32952 page 48 ...

Page 49: ...PX P3 D9 32 33 NC XMC_1_F13 To VPX P3 A9 34 35 NC XMC_1_C14 To VPX P3 F10 36 37 NC XMC_1_F14 To VPX P3 C10 38 39 NC XMC_1_C15 To VPX P3 E10 40 41 NC XMC_1_F15 To VPX P3 B10 42 43 NC XMC_1_C16 To VPX P3 E11 44 45 NC XMC_1_F16 To VPX P3 B11 46 47 NC XMC_1_C17 To VPX P3 D11 48 49 NC XMC_1_F17 To VPX P3 A11 50 51 NC XMC_1_C18 To VPX P3 F12 52 53 NC XMC_1_F18 To VPX P3 C12 54 55 NC XMC_1_C19 To VPX P3 ...

Page 50: ...5 XMC_2_F16 32 33 XMC_2_C16 XMC_2_F17 34 35 XMC_2_C17 XMC_2_F18 36 37 XMC_2_C18 XMC_2_F19 38 39 XMC_2_C19 PXMC_2_ID_0 40 41 PXMC_2_ID_1 XMC_2_C1 To VPX P5 B3 42 43 NC XMC_2_F1 To VPX P5 A3 44 45 NC XMC_2_C2 To VPX P5 F4 46 47 NC XMC_2_F2 To VPX P5 C4 48 49 NC XMC_2_C3 To VPX P5 E4 50 51 NC XMC_2_F3 To VPX P5 B4 52 53 NC XMC_2_C4 To VPX P5 E5 54 55 NC XMC_2_F4 To VPX P5 B5 56 57 NC XMC_2_C5 To VPX ...

Page 51: ...hese two pins are module identification pins These signals may be read by the microcontroller The XMC X38s module IM3500 0000 ID pins are read as 00 respectively VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Property of Rigel Engineering LLC Confidential Proprietary 690 Cone Park Court Merritt Island Florida 32952 page 51 ...

Page 52: ...PX P5 D9 32 33 NC XMC_2_F13 To VPX P5 A9 34 35 NC XMC_2_C14 To VPX P5 F10 36 37 NC XMC_2_F14 To VPX P5 C10 38 39 NC XMC_2_C15 To VPX P5 E10 40 41 NC XMC_2_F15 To VPX P5 B10 42 43 NC XMC_2_C16 To VPX P5 E11 44 45 NC XMC_2_F16 To VPX P5 B11 46 47 NC XMC_2_C17 To VPX P5 D11 48 49 NC XMC_2_F17 To VPX P5 A11 50 51 NC XMC_2_C18 To VPX P5 F12 52 53 NC XMC_2_F18 To VPX P5 C12 54 55 NC XMC_2_C19 To VPX P5 ...

Page 53: ... J12 and J13 make up the standard 64 bit PCI X bus and J14 has user defined IO signals which depends on what the PMC card supports The J14 IO signals are routed to backplane connector P3 per VITA 46 9 P64s Compare Tables 25 26 to Table 20 below for J14 to see how these IO signals are mapped The tables on the following pages illustrate the pinout for the PMC 1 connectors as defined on the VP3500 VP...

Page 54: ...37 DEVSEL_L 5V 38 39 PCIXCAP LOCK_L 40 41 SDONE_L SBO_L 42 43 PAR GND 44 45 3 3V VIO AD15 46 47 AD12 AD11 48 49 AD9 5V 50 51 GND CBE0 52 53 AD6 AD5 54 55 AD4 GND 56 57 3 3V VIO AD3 58 59 AD2 AD1 60 61 AD0 5V 62 63 GND REQ64_L 64 Table 17 PMC 1 J11 Connector pin out Rose Standard PCI or PCI X signals 3 3V VIO PMC IO Signaling voltage on the VP3500 VP3500 User Manual Document Number 101 3500 0001 Re...

Page 55: ...2 43 CBE1 GND 44 45 AD14 AD13 46 47 66EN AD10 48 49 AD8 3 3V 50 51 AD7 REQA_L 52 53 3 3V GNTA_L 54 55 NC GND 56 57 NC EREADY 58 59 GND NC 60 61 ACK64_L 3 3V 62 63 GND NC 64 Table 18 PMC 1 J12 Connector pin out Rose Standard PCI or PCI X signals BMODE 4 3 2 These input signals to the PMC are set to 001 by the VP3500 respectively This should return PMC module present status from the PMC VP3500 User ...

Page 56: ... 35 AD47 AD46 36 37 AD45 GND 38 39 3 3V AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 3 3V AD32 58 59 NC NC 60 61 NC GND 62 63 GND NC 64 Table 19 PMC 1 J13 Connector pin out Rose Standard PCI or PCI X signals VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Property of Rigel Engineering LLC Confident...

Page 57: ... 42 43 PMC_1_43 PMC_1_44 44 45 PMC_1_45 PMC_1_46 46 47 PMC_1_47 PMC_1_48 48 49 PMC_1_49 PMC_1_50 50 51 PMC_1_51 PMC_1_52 52 53 PMC_1_53 PMC_1_54 54 55 PMC_1_55 PMC_1_56 56 57 PMC_1_57 PMC_1_58 58 59 PMC_1_59 PMC_1_60 60 61 PMC_1_61 PMC_1_62 62 63 PMC_1_63 PMC_1_64 64 Table 20 PMC 1 J14 Connector pin out PMC_1 VITA 46 9 P64s Single ended J14 IO direct routing from PMC 1 J14 to VPX P3 PMC_1 VITA 46 ...

Page 58: ...3 3V VIO AD17 32 33 FRAME_L GND 34 35 GND IRDY_L 36 37 DEVSEL_L 5V 38 39 PCIXCAP LOCK_L 40 41 SDONE_L SBO_L 42 43 PAR GND 44 45 3 3V VIO AD15 46 47 AD12 AD11 48 49 AD9 5V 50 51 GND CBE0 52 53 AD6 AD5 54 55 AD4 GND 56 57 3 3V VIO AD3 58 59 AD2 AD1 60 61 AD0 5V 62 63 GND REQ64_L 64 Table 21 PMC 2 J21 Connector pin out Rose Standard PCI or PCI X signals 3 3V VIO PMC IO Signaling voltage on the VP3500...

Page 59: ...ERR_L 42 43 CBE1 GND 44 45 AD14 AD13 46 47 66EN AD10 48 49 AD8 3 3V 50 51 AD7 REQA_L 52 53 3 3V GNTA_L 54 55 NC GND 56 57 NC EREADY 58 59 GND NC 60 61 ACK64_L 3 3V 62 63 GND NC 64 Table 22 PMC 2 J22 Connector pin out Rose Standard PCI or PCI X signals BMODE 4 3 2 These input signals to the PMC are set to 001 respectively This should return PMC module present status from the PMC VP3500 User Manual ...

Page 60: ... 35 AD47 AD46 36 37 AD45 GND 38 39 3 3V AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 3 3V AD32 58 59 NC NC 60 61 NC GND 62 63 GND NC 64 Table 23 PMC 2 J23 Connector pin out Rose Standard PCI or PCI X signals VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Property of Rigel Engineering LLC Confident...

Page 61: ... 42 43 PMC_2_43 PMC_2_44 44 45 PMC_2_45 PMC_2_46 46 47 PMC_2_47 PMC_2_48 48 49 PMC_2_49 PMC_2_50 50 51 PMC_2_51 PMC_2_52 52 53 PMC_2_53 PMC_2_54 54 55 PMC_2_55 PMC_2_56 56 57 PMC_2_57 PMC_2_58 58 59 PMC_2_59 PMC_2_60 60 61 PMC_2_61 PMC_2_62 62 63 PMC_2_63 PMC_2_64 64 Table 24 PMC 2 J24 Connector pin out PMC_2 VITA 46 9 P64s Single ended J24 IO direct routing from PMC 2 J24 to VPX P5 PMC_2 VITA 46 ...

Page 62: ...e section 3 3 3 for additional information regarding the XMC IO Module The following tables describe the single ended signal mapping for both PMC slots when using Rigel model number IM3500 0001 IO module Figure 8 IO Module Figure 9 IO Module Mounted on VP3500 VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Property of Rigel Engineering LLC Confidential Proprietary 690 Cone Park Court M...

Page 63: ... 50 51 PMC_1_IO_15 PMC_1_IO_16 To VPX P3 B4 52 53 PMC_1_IO_16 PMC_1_IO_17 To VPX P3 E5 54 55 PMC_1_IO_17 PMC_1_IO_18 To VPX P3 B5 56 57 PMC_1_IO_18 PMC_1_IO_19 To VPX P3 D5 58 59 PMC_1_IO_19 GND 60 Table 25 PMC 1 IO Module connector 1 pin mapping PMC_1 VITA 46 9 P64s single end signals from PMC slot 1 J14 PMC_1 VITA 46 9 P64s single end signals to VPX connector P3 PXMC_1_ID_1 0 These two pins are ...

Page 64: ... 33 PMC_1_IO_35 PMC_1_IO_36 To VPX P3 A9 34 35 PMC_1_IO_36 PMC_1_IO_37 To VPX P3 F10 36 37 PMC_1_IO_37 PMC_1_IO_38 To VPX P3 C10 38 39 PMC_1_IO_38 PMC_1_IO_39 To VPX P3 E10 40 41 PMC_1_IO_39 PMC_1_IO_40 To VPX P3 B10 42 43 PMC_1_IO_40 PMC_1_IO_41 To VPX P3 E11 44 45 PMC_1_IO_41 PMC_1_IO_42 To VPX P3 B11 46 47 PMC_1_IO_42 PMC_1_IO_43 To VPX P3 D11 48 49 PMC_1_IO_43 PMC_1_IO_44 To VPX P3 A11 50 51 P...

Page 65: ... 50 51 PMC_2_IO_15 PMC_2_IO_16 To VPX P5 B4 52 53 PMC_2_IO_16 PMC_2_IO_17 To VPX P5 E5 54 55 PMC_2_IO_17 PMC_2_IO_18 To VPX P5 B5 56 57 PMC_2_IO_18 PMC_2_IO_19 To VPX P5 D5 58 59 PMC_2_IO_19 GND 60 Table 27 PMC 2 IO Module connector 1 pin mapping PMC_2 VITA 46 9 P64s single end signals from PMC slot 2 J24 PMC_2 VITA 46 9 P64s single end signals to VPX connector P5 PXMC_2_ID_1 0 These two pins are ...

Page 66: ... 33 PMC_2_IO_35 PMC_2_IO_36 To VPX P5 A9 34 35 PMC_2_IO_36 PMC_2_IO_37 To VPX P5 F10 36 37 PMC_2_IO_37 PMC_2_IO_38 To VPX P5 C10 38 39 PMC_2_IO_38 PMC_2_IO_39 To VPX P5 E10 40 41 PMC_2_IO_39 PMC_2_IO_40 To VPX P5 B10 42 43 PMC_2_IO_40 PMC_2_IO_41 To VPX P5 E11 44 45 PMC_2_IO_41 PMC_2_IO_42 To VPX P5 B11 46 47 PMC_2_IO_42 PMC_2_IO_43 To VPX P5 D11 48 49 PMC_2_IO_43 PMC_2_IO_44 To VPX P5 A11 50 51 P...

Page 67: ...rm to PCI Express Mini Card Electromechanical Specification Revision 1 2 Each socket includes an IO connector located off the farthest Mini Card PCB edge This allows for a custom PCB design that would interface the Mini Card s IO to the VPX backplane These connectors are covered in section 3 6 Figure 10 MiniPCIe Sockets VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Property of Rigel ...

Page 68: ...D NC 36 37 GND NC 38 39 3 3V GND 40 41 3 3V LED_WWAN_L 42 43 GND LED_WLAN_L 44 45 NC LED_WPAN_L 46 47 NC 1 5V 48 49 NC GND 50 51 NC 3 3V 52 Table 29 MiniPCIe socket 1 pin out REF_CLK 100 MHz differential reference clock inputs to the MiniPCIe card MPCIE1_PER PCI Express differential receive signals driven from the MiniPCIe card MPCIE1_PET PCI Express differential transmit signals driven from the V...

Page 69: ...card When the MiniPCIe card drives this signal low it illuminates the yellow LED to signify that a wireless wide area network cellular data card is installed or active LED_WLAN_L This optional open drain output signal from a MiniPCIe card is connected to a green LED that is mounted on the VP3500 that is located by the add in card When the MiniPCIe card drives this signal low it illuminates the gre...

Page 70: ...V LED_WWAN_L 42 43 GND LED_WLAN_L 44 45 NC LED_WPAN_L 46 47 NC 1 5V 48 49 NC GND 50 51 NC 3 3V 52 Table 30 MiniPCIe socket 2 pin out REF_CLK 100 MHz differential reference clock inputs to the MiniPCIe card MPCIE2_PER PCI Express differential receive signals driven from the MiniPCIe card MPCIE2_PET PCI Express differential transmit signals driven from the VP3500 to the MiniPCIe card VP3500 User Man...

Page 71: ...ard When the MiniPCIe card drives this signal low it illuminates the yellow LED to signify that a wireless wide area network cellular data card is installed or active LED_WLAN_L This optional open drain output signal from a MiniPCIe card is connected to a green LED mounted on the VP3500 that is located by the add in card When the MiniPCIe card drives this signal low it illuminates the green LED to...

Page 72: ...or supports 20 differential and 8 single ended signals routed to the backplane Figure 11 MiniPCIe IO Module Locations The tables on the following pages define how the signals are routed between the MiniPCIe IO Module connectors and the VPX backplane MiniPCIe 1 Rear IO Adapter Connector MiniPCIe 2 Rear IO Adapter Connector Pin 1 Pin 2 VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Prop...

Page 73: ...VPX P2 F6 36 37 GND GND 38 39 VPX P2 A7 MP1_DX12 MP1_DX13 VPX P2 D7 40 41 VPX P2 B7 MP1_DX12 MP1_DX13 VPX P2 E7 42 43 GND GND 44 45 VPX P2 B8 MP1_DX14 MP1_DX15 VPX P2 E8 46 47 VPX P2 C8 MP1_DX14 MP1_DX15 VPX P2 F8 48 49 GND GND 50 51 VPX P6 A11 MP1_DX16 MP1_DX17 VPX P6 D11 52 53 VPX P6 B11 MP1_DX16 MP1_DX17 VPX P6 E11 54 55 GND GND 56 57 VPX P6 B12 MP1_DX18 MP1_DX19 VPX P6 E12 58 59 VPX P6 C12 MP1...

Page 74: ...routed as differential pairs on the VP3500 MP1_SE These are the single ended user defined signals that are directly routed from the MiniPCIe 1 IO connector to VPX connectors P2 and P6 VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Property of Rigel Engineering LLC Confidential Proprietary 690 Cone Park Court Merritt Island Florida 32952 page 74 ...

Page 75: ...1 VPX P2 F14 36 37 GND GND 38 39 VPX P2 A15 MP2_DX12 MP2_DX13 VPX P2 D15 40 41 VPX P2 B15 MP2_DX12 MP2_DX13 VPX P2 E15 42 43 GND GND 44 45 VPX P2 B16 MP2_DX14 MP2_DX15 VPX P2 E16 46 47 VPX P2 C16 MP2_DX14 MP2_DX15 VPX P2 F16 48 49 GND GND 50 51 VPX P6 A13 MP2_DX16 MP2_DX17 VPX P6 D13 52 53 VPX P6 B13 MP2_DX16 MP2_DX17 VPX P6 E13 54 55 GND GND 56 57 VPX P6 B14 MP2_DX18 MP2_DX19 VPX P6 E14 58 59 VPX...

Page 76: ...routed as differential pairs on the VP3500 MP2_SE These are the single ended user defined signals that are directly routed from the MiniPCIe 2 IO connector to VPX connectors P2 and P6 VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Property of Rigel Engineering LLC Confidential Proprietary 690 Cone Park Court Merritt Island Florida 32952 page 76 ...

Page 77: ...eded or failures and or damage to the product may occur Environmental Specifications Operating Temperature Commercial 0 to 70 C ambient 300 LFM Minimum forced air Extended 40 to 85 C ambient 300 LFM Minimum forced air Conduction cooled 40 to 85 C measured at the rail Storage Temperature All Models 40 to 85 C Humidity All Models 0 95 non condensing Shock Operating Air cooled 20g 11ms saw tooth Cond...

Page 78: ...the switch PCIe Switch Specifications MiniPCIe Socket 1 PEX 8648 Station 0 Port 0 PCIe Lane 0 MiniPCIe Socket 2 PEX 8648 Station 0 Port 1 PCIe Lane 4 PCIe to PCI PMC Bridge 1 PEX 8648 Station 0 Port 2 PCIe Lanes 8 11 PCIe to PCI PMC Bridge 2 PEX 8648 Station 0 Port 3 PCIe Lanes 12 15 VPX P1 Fabric A PEX 8648 Station 1 Port 4 PCIe Lanes 16 19 Default Upstream VPX P1 Fabric B PEX 8648 Station 1 Port...

Page 79: ...IO Access Air Cooled Front panel or VPX Rear IO VITA 46 9 P64S with IO module Conduction Cooled Front panel or VPX Rear IO VITA 46 9 P64S with IO module Table 38 PMC Specifications 4 7 VPX Fabric Specifications The VP3500 uses VPX P1 fabrics A B C and D to form 4 PCIe FAT pipes capable of PCIe Gen 2 Gen 1 compatible This 4x4 configuration is the board s default at power up The configuration may be...

Page 80: ...ntegrated VITA 46 6 standard Gigabit Ethernet Switch The VP3500 switch includes five total GbE ports Two of the five ports are VITA 46 6 auto negotiating 10 100 1000 and are configured as 1000BASE T with on board magnetics The other two VITA 46 6 ports are configured as 1000BASE BX for backplane applications The remaining port is a third 1000BASE T routed to P6 that may be used as a maintenance po...

Page 81: ...ont panel The Figure below illustrates a front view of the VP3500 with the LEDs on the bottom side of the board Fatal Error PCIe Port 9 PCIe Port 8 PCIe Port 7 PCIe Port 6 PCIe Port 5 PCIe Port 4 PCIe Port 3 PCIe Port 2 PCIe Port 1 PCIe Port 0 GbE Int GbE Port 5 Link Active GbE Port 4 Link Active GbE Port 2 Link Active GbE Port 2 100Mb Link GbE Port 2 1Gb Link GbE Port 1 Link Active GbE Port 1 100...

Page 82: ...ASE T Yellow This LED indicates port 1 of the Ethernet switch has established a 100Mb link GbE Port 1 Activity VITA 46 6 1000BASE T Green This LED indicates port 1 of the Ethernet switch is currently transmitting or receiving data GbE Port 2 1Gb Link GP GbE routed to VPX P6 Green This LED indicates port 2 of the Ethernet switch has established a 1Gb link GbE Port 2 100Mb Link GP GbE routed to VPX ...

Page 83: ...es PCIe link status with VPX Port 1 This PCIe port is configured as a x4 Supports Gen 1 2 PCIe Port 6 Link Status VPX Port 2 Green This LED indicates PCIe link status with VPX Port 2 This PCIe port is configured as a x4 Supports Gen 1 2 PCIe Port 7 Link Status VPX Port 3 Green This LED indicates PCIe link status with VPX Port 3 This PCIe port is configured as a x4 Supports Gen 1 2 PCIe Port 8 Link...

Page 84: ...vice may be reconfigured by the on board microcontroller as well For example the default VPX port setting is 4x4 That configuration may be changed to meet system requirements to a 1x16 or 2x8 Please see section 5 3 The below figure illustrates the default PCIe Switch configuration as implemented on the VP3500 Port 0 x1 Mini PCIe 1 Mini PCIe 2 Port 1 x1 PCI Bridge 1 Port 2 x4 PCI Bridge 2 Port 3 x4...

Page 85: ...through the standard RS 232 serial connector J11 on the RTM RT3500 0000 or by the on board header HDR3 The port is configured as RS 232 9600 8 bits no parity 1 stop bit The following figures illustrate the pinouts Figure 14 RT3500 Microcontroller Serial Connector Figure 15 VP3500 Microcontroller Serial Connector HDR3 Pin Signal 1 4 6 7 8 9 No Connects 2 RS 232 Receive data to microcontroller 3 RS ...

Page 86: ...ata to EEPROM h Help i VP3500 Board Specific Information m MiniPCIe Select p Toggle Board Power On Off r Read Data From I2C Device s VP3500 Board Status w Write Data to I2C Device Table 46 Microcontroller Serial Port Commands Please reference section 5 4 for additional information regarding the VP3500 I2C structure 5 3 2 1 Select I2C Bus The VP3500 has four local I2C buses See section 5 4 for more...

Page 87: ...ress 0x4c is set Awrite to the device is performed to set its internal address pointer 0x00 and finally the read is performed and the result is displayed 0x5E 1 a Enter the new I2C address 4c w Enter the data to write 00 r Data read from I2C 0x5E 5 3 2 4 Raw I2C Write Write one or more bytes to the local I2C bus After entering the w command a prompt will appear to enter the data to write The data ...

Page 88: ...luding power status current temperature and the population status of the PMC XMC sites s Temperature 30 C Temp Alert FALSE Temp Alert Low 0 Temp Alert High 70 Power Good VCC 3 3 TRUE VCC 2 5 TRUE VCC 1 8 TRUE VCC 1 5 TRUE VCC 1 0B TRUE VCC 1 0S TRUE P XMC Site 1 Present NO I O Module NONE BIST 46 FALSE MRSTO FALSE P XMC Site 2 Present NO I O Module NONE BIST FALSE MRSTO FALSE VP3500 User Manual Do...

Page 89: ...est 256 bytes Bank 0 of the EEPROM After entering the command a prompt will be displayed to enter the address The address must be entered as two hexadecimal characters e Enter the address to read 00 Data read from EEPROM 0xA5 5 3 2 10 Write EEPROM The f command will write a single byte to any of the lowest 256 bytes Bank 0 of the EEPROM After entering the command a prompt will be displayed to ente...

Page 90: ...97 R Status PCIe Port 7 Status 0x98 R Status PCIe Port 8 Status 0x99 R Status PCIe Port 9 Status 0xA0 W Address W Data EEPROM Bank 0 Write 0xA1 W Address R Data EEPROM Bank 0 Read 0xA2 W Address W Data EEPROM Bank 1 Write 0xA3 W Address R Data EEPROM Bank 1 Read 0xA4 W Address W Data EEPROM Bank 2 Write 0xA5 W Address R Data EEPROM Bank 2 Read 0xA6 W Address W Data EEPROM Bank 3 Write 0xA7 W Addre...

Page 91: ... Slave 0xF9 W Data I2C Raw Write 0xFA R Data I2C Raw Read Table 47 Microcontroller VPX Commands 5 3 3 1 Read Power Status Bits Detail 0 VCC 1 0 S Power Good 1 VCC 1 0 B Power Good 2 VCC 1 5 Power Good 3 VCC 1 8 Power Good 4 VCC 2 5 Power Good 5 VCC 3 3 Power Good 6 Reserved 7 Power On Table 48 Power Status Read power status i2cget y 1 0x5a 0x82 0xbf Turn off power i2cget y 1 0x5a 0x81 Read power s...

Page 92: ...0x5a xxd r sn i2cget y 1 0x5a xxd r echo sn 1332010006 5 3 3 3 PEX8648 PCIe Switch Port 0 9 Status Bits Detail 4 0 Number of PCIe lanes up 6 5 Speed 01 Gen 1 10 Gen 2 7 Reserved Table 49 PCIe Switch Port Status Read port 4 status 4 lanes at Gen 2 speed i2cget y 1 0x5a 0x94 0x44 VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Property of Rigel Engineering LLC Confidential Proprietary 69...

Page 93: ...a range of 64 to 191 C however the capability of the sensor is only from 40 to 100 C Read the board temperature 0x5d 93 64 29 C i2cget y 1 0x5a 0xb0 0x5d 5 3 3 6 Set High Low Alert Temperature Limits Temperature limit values are also in the extended binary offset format of the ADT7461 Take the desired temperature limit add 64 and convert it to hexadecimal Set upper temperature alert limit to 85 C ...

Page 94: ...isable wireless on MiniPCIe socket 1 i2cget y 1 0x5a 0xd1 Enable wireless on MiniPCIe socket 2 i2cget y 1 0x5a 0xd2 5 3 3 9 MiniPCIe Wireless Status Bits Detail 0 MiniPCIe 1 Wireless Enabled 1 MiniPCIe 2 Wireless Enabled 7 2 Reserved Table 51 MinePCIe Wireless Status Read MiniPCIe status MiniPCIe 1 wireless disabled MiniPCIe 2 wireless enabled i2cget y 1 0x5a 0xd4 0x02 VP3500 User Manual Document ...

Page 95: ...et y 1 0x5a 0x00 5 3 3 11 I2C Bus Select 1 4 Select local I2C bus 2 i2cget y 1 0x5a 0xf2 5 3 3 12 I2C Slave Address Set the currently selected I2C slave address to 0x4C i2cget y 1 0x5a 0xf8 i2cget y 1 0x5a 0x4c 5 3 3 13 Raw I2C Read Write Here is an example using raw I2C read and write commands to read the temperature i2cget y 1 0x5a 0xf1 i2cget y 1 0x5a 0xf8 i2cget y 1 0x5a 0x4c i2cget y 1 0x5a 0...

Page 96: ...v i serial_number 0 0 if i2c_addr 0 open I2C device i2c_dev open dev i2c 1 O_RDWR ioctl i2c_dev I2C_SLAVE i2c_addr i 0 if i2c_dev 0 i2c_smbus_write_byte i2c_dev 0x84 for i 0 i 11 i serial_number i char i2c_smbus_read_byte i2c_dev close i2c_dev serial_number i 0 VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Property of Rigel Engineering LLC Confidential Proprietary 690 Cone Park Court...

Page 97: ...ards The below block diagram details the I2C busses devices and their addresses IPMBA 4 MP2 I2C 1 PLT I2C 2 EEP I2C V P X Microcontroller I2C Switch E0 E1 Temp Sensor 98 99 PCIe Clock D8 D9 PCIe Switch D2 D3 XMC 1 A0 A1 XMC 2 A8 A9 EEPROM A0 A7 3 MP1 I2C MiniPCIe 1 xx xx MiniPCIe 2 xx xx Figure 16 VP3500 I2C Topology VP3500 User Manual Document Number 101 3500 0001 RevisionA0 Property of Rigel Eng...

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