VRESET_L
This low-true input pin is the system reset signal. The VP3500 receives this signal to reset the board.
NVMRO
(Non-Volatile Memory Read Only) A system wide signal which, when asserted, prevents any non-volatile
memory from being updated. This allows systems with security sensitivity the ability to run classified or
sensitive data without the concern that the data will be kept over power cycles. This also supports the
updating or protection of program store memory.
This high-true input signal to the VP3500 is routed to the NVMRO pins on each XMC connector and the
on-board EEPROM write protect pin.
/-
These 1 PPS differential input signals to the VP3500 are translated to LVTTL levels then routed to each
XMC/PMC IO module.
This reference timing source is defined with relatively tight accuracy and stability specifications and is
driven differentially on the backplane in order to provide high signal integrity. This signal is typically used
in OpenVPX applications to provide a high-precision hardware timing delimiter for time-based processing
tasks.
VP3500 User Manual • Document Number 101-3500-0001 • Revision A0
Property of Rigel Engineering, LLC. Confidential & Proprietary
690 Cone Park Court, Merritt Island, Florida 32952
page 30
