RDC R8810LV, User Manual

Page: 20 / 93

RDC
®
RISC DSP Controller
R8810LV
RDC Semiconductor Co.
Rev:1.1
Subject to change without notice
20
Peripheral Control Block Register
The peripheral control block can be mapped into either memory or I/O space which is to program the FEh register. And it
starts at FF00h in I/O space when reset the microprocessor.
The following table is the definition of all the peripheral Control Block Register , and the detail description will arrange on
the relation Block Unit.
Offset
(HEX)
Register Name Page
Offset
(HEX)
Register Name Page
FE Peripheral Control Block Relocation Register 21 66 Timer 2 Mode / Control Register 60
F6 Reset Configuration Register 24 62 Timer 2 Maxcount Compare A Register 61
F4 Processor Release Level Register 21 60 Timer 2 Count Register 61
F0 PDCON Register 22 5E Timer 1 Mode / Control Register 58
E4 Enable RCU Register 74 5C Timer 1 Maxcount Compare B Register 60
E2 Clock Prescaler Register 74 5A Timer 1 Maxcount Compare A Register 60
E0 Memory Partition Register 74 58 Timer 1 Count Register 60
DA DMA 1 Control Register 52 56 Timer 0 Mode / Control Register 57
D8 DMA 1 Transfer Count Register 54 54 Timer 0 Maxcount Compare B Register 58
D6 DMA 1 Destination Address High Register 54 52 Timer 0 Maxcount Compare A Register 58
D4 DMA 1 Destination Address Low Register 54 50 Timer 0 Count Register 57
D2 DMA 1 Source Address High Register 55 44 Serial Port Interrupt Control Register 37
D0 DMA 1 Source Address Low Register 55 42 Watchdog Timer Control Register 61
CA DMA 0 Control Register 51 40 INT4 Control Register 38
C8 DMA 0 Transfer Count Register 51 3E INT3 Control Register 39
C6 DMA 0 Destination Address High Register 51 3C INT2 Control Register 39
C4 DMA 0 Destination Address Low Register 52 3A INT1 Control Register 40
C2 DMA 0 Source Address High Register 52 38 INT0 Control Register 40
C0 DMA 0 Source Address Low Register 52 36 DMA 1 Interrupt Control Register 41
A8
PCS and MCS Auxiliary Register
32 34 DMA 0 Interrupt Control Register 42
A6 Midrange Memory Chip Select Register 31 32 Timer Interrupt Control Register 42
A4 Peripheral Chip Select Register 33 30 Interrupt Status Register 43
A2 Low Memory Chip Select Register 30 2E Interrupt Request Register 44
A0 Upper Memory Chip Select Register 29 2C In-service Register 45
88 Serial Port Baud Rate Divisor Register 66 2A Priority Mask Register 46
86 Serial Port Receive Register 65 28 Interrupt Mask Register 47
84 Serial Port Transmit Register 65 26 Poll Status Register 47
82 Serial Port Status Register 64 24 Poll Register 48
80 Serial Port Control Register 63 22 End-of-Interrupt 48
7A PIO Data 1 Register 72 20 Interrupt Vector Register 49
78 PIO Direction 1 Register 72 18 Synchronous Serial Receive Register 68
76 PIO Mode 1 Register 72 16 Synchronous Serial Transmit 0 Register 68
74 PIO Data 0 Register 73 14 Synchronous Serial Transmit 1 Register 68
72 PIO Direction 0 Register 73 12 Synchronous Serial Enable Register 67
70 PIO Mode 0 Register 73 10 Synchronous Serial Status Register 67