RDC
®
RISC DSP Controller
R8810LV
RDC Semiconductor Co.
Rev:1.2
Subject to change without notice
43
Bit 3: MSK
, Mask.
Set 1: Mask the interrupt source of the Timer controller
Set 0: Enable the Timer controller interrupt.
Bit 2-0: PR
, Interrupt Priority
These bits setting for priority selection is same as bit 2-0 of the register 44h
(Slave Mode), Timer 0 Interrupt Control Register,
reset value is 0000h
Bit 15-4
: Reserved
Bit 3: MSK
, Mask.
Set 1: Mask the interrupt source of the Timer 0 controller
Set 0: Enable the Timer 0 controller interrupt.
Bit 2-0: PR
, Interrupt Priority
These bits setting for priority selection is same as bit 2-0 of the register 44h
(Master Mode),
Reset value un-define
Bit 15 : DHLT
, DMA Halt.
Set 1: halts any DMA activity. When non-maskable interrupts occur.
Set 0: When an IRET instruction is executed.
Bit 14-3 :
Reserved.
Bit 2-0 : TMR2-TMR0
,
Set 1: indicates the corresponding timer has an interrupt request pending.
(Slave Mode),
Reset value is 0000h
Bit 15 : DHLT
, DMA Halt.
Set 1: halts any DMA activity. When non-maskable interrupts occur.
Set 0: When an IRET instruction is executed.
Bit 14-3 :
Reserved.
Bit 2-0 : TMR2-TMR0
,
Set 1: indicates the corresponding timer has an interrupt request pending.
Interrupt Status Register
Offset : 30h
0
Reset Value :
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Reserved
TMR2 TMR1 TMR0
DHLT