RDC R8810LV User Manual Download Page 65

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RDC

RISC DSP Controller

R8810LV

RDC Semiconductor Co.

Rev:1.2

Subject to change without notice

can not be written a new data.

When the transmit interrupt is enabled, a serial port interrupt is generated when this bit is 1. The THRE bit is

automatically cleared by H/W during copy data to transmit holding buffer.

Bit 4: RDR

, Receive Data Ready. Read only bit. When the receive data register is ready to read, this bit is 1. When the bit is

0, the receive data register dose not contain valid data. This bit will be cleared by H/W when reading the receive data

Bit 3: BRKI

, Break Interrupt. It indicates that a break has been receive when this bit is set 1 and it will generate a serial pot

interrupt request if the RISE bit (80h.1) is enabled. This bit is set by H/W and should be cleared by software.

Bit 2: FER

, Framing Error. This bit is set to indicate that a framing error occurred during reception of data and it will

generate a serial pot interrupt request if the RISE bit (80h.1) is enabled. This bit is set by H/W and should be cleared by

software.

Bit 1: PER

, Parity Error. This bit is set to indicate that a party error occurred during reception of data and it will generate a

serial pot interrupt request if the RISE bit (80h.1) is enabled. This bit is set by H/W and should be cleared by software.

Bit 0: OER

, Overrun Error. This bit is set to indicate that a overrun error occurred during reception of data and it will

generate a serial port interrupt request if the RISE bit (80h.1) is enabled. This bit is set by H/W and should be cleared

by software.

Bit 15-8

: Reserved

Bit 7-0

: TDATA, Transmit Data. Software writes this register with data to be transmitted on the serial port.

The THRE bit (82h.5) should be read as a 1 before writing this register to avoid overwriting data to this register.

When writing data to this register, the THRE bit will be cleared by H/W in the same time.

Bit 15-8

: Reserved

Bit 7-0: RDATA

, Received DATA. The PDR bit (82h.4) should be read as 1 before read the RDATA register to avoid reading

invalid data.

Offset : 84h

Reset Value :

Reserved

Serial Port Transmit Data Register

TDATA

Offset : 86h

Reset Value :

Reserved

Serial Port Receive Data Register

RDATA

Summary of Contents for R8810LV

Page 1: ...810LV RDC Semiconductor Co Rev 1 2 Subject to change without notice 1 R8810LV 16 Bit RISC Microcontroller User s Manual RDC RISC DSP Controller RDC Semiconductor Co Ltd http www rdc com tw Tel 886 3 6...

Page 2: ...ecution Unit 17 General Register 17 Segment Register 17 Instruction Pointer and Status Flags Register 18 Address Generation 19 Peripheral Control Block Register 20 System Clock Block 22 Reset 23 Bus I...

Page 3: ...chdog Timer 61 Timer Counter Unit Output Mode 62 Asynchronous Serial Port 63 Synchronous Serial Port 67 Synchronous Serial Port Operation 69 PIO Unit 71 PIO Multi Function Pin list Table 71 PSRAM Cont...

Page 4: ...five maskable external interrupts and one nonmaskable external interrupt l Two independent DMA channels l Programble chip select logic for Memory or I O bus cycle decoder l Programmable wait state ge...

Page 5: ...SCLK PIO20 ALE ARDY GND X1 X2 VCC CLKOUTA CLKOUTB GND A19 PIO9 A18 PIO8 VCC A17 PIO7 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 VCC A0 GND GND HLDA HOLD SRDY PIO6 NMI INT4 PIO30 INT0 VCC...

Page 6: ...GND HOLD HLDA SRDY PIO6 NMI INT4 PIO30 INT0 VCC GND VCC GND TMRIN1 PIO0 TMROUT0 PIO10 TMRIN0 PIO11 TMROUT1 PIO1 DRQ1 PIO13 DRQ0 PIO12 GND DT R PIO4 INT3 INTA1 IRQ INT2 INTA0 PIO31 INT1 SELECT UCS ONC...

Page 7: ...99 DEN PI O5 72 49 SDATA PI O21 23 100 0 MCS PI O14 73 50 SDEN1 PI O23 24 1 1 MCS PI O15 74 51 SDEN0 PI O22 25 2 I NT4 PI O30 75 52 SCLK PI O20 26 3 I NT3 1 INTA I RQ 76 53 2 RFSH ADEN 27 4 I NT2 0 IN...

Page 8: ...ATA PIO21 Input Output Synchronous serial data This pin provides the shift data to or receives a serial data from an external device Asynchronous Serial Port Interface 98 TXD PIO27 Output Input Transm...

Page 9: ...I O address The A bus is one half of a CLKOUTA period earlier than the AD bus These pins are high impedance during bus hold or reset 78 80 82 84 86 88 91 94 AD0 AD7 Input Output The multiplexed addres...

Page 10: ...ed bus cycle or high to indicate a DMA initiated bus cycle during T2 T3 Tw and T4 For 2 CLKDIV feature The internal clock of microcontroller is the external clock be divided by 2 CLKOUTA CLKOUTB X1 2...

Page 11: ...e microcontroller always transfers the address bus to the location specified by the nonmaskable interrupt vector in the microcontroller interrupt vector table The NMI pin must be asserted for at least...

Page 12: ...troller increments These pins must be pull up if not being used 73 74 TMROUT1 PIO1 TMROUT0 PIO10 Output Input Timer output Depending on timer mode select these pins provide single pulse or continuous...

Page 13: ...Data 8 Address SRAM Data Address WE OE Peripheral CS PCSx R8810LV WE OE CE LCS BASIC APPLICATION SYSTEM BLOCK B RST VCC 100K 1uF DIR Transciver G Latch DEN DT R AD7 AD0 AD7 AD0 ALE AO15 AO8 A19 A16 X1...

Page 14: ...otice 14 Oscillator Characteristics For fundamental mode crystal C1 20pF 20 C2 20pF 20 Rf 1 mega ohm C3 L Don t care For third overtone mode crystal C1 20pF 20 C2 20pF 20 C3 200pf Rf 1 mega ohm L 3 0u...

Page 15: ...RDC Semiconductor Co Rev 1 1 Subject to change without notice 15 Read Write timing Diagram CLKOUTA A19 A0 S6 AO15 AO8 ALE DEN DT R UZI T1 T2 T3 T4 ADDRESS UCS LCS S2 S0 TW READ CYCLE PCSx MCSX ADDRES...

Page 16: ...ler R8810LV RDC Semiconductor Co Rev 1 1 Subject to change without notice 16 CLKOUTA A19 A0 S6 AO15 AO8 ALE WR DEN DT R UZI T1 T2 T3 T4 ADDRESS UCS LCS S2 S0 TW WRITE CYCLE PCSx MCSX ADDRESS AD7 AD0 W...

Page 17: ...PA POPF PUSH PUSHA PUSHF BP General purpose register which can be used to determine offset address of operands in Memory SI String operations DI String operations Segment Register R8810 has four 16 bi...

Page 18: ...ess the IP register and this register is updated by the Bus Interface Unit It can change be saved or be restored as a result of program execution The IP register initialize to 0000H and the CS IP star...

Page 19: ...the low nibble to the high or a borrow from the high nibble to the low nibble of the AL general purpose register Used in BCD operation Bit 3 Reserved Bit 2 PF Parity Flag The result of low order 8 bit...

Page 20: ...ster 37 D0 DMA 1 Source Address Low Register 55 42 Watchdog Timer Control Register 61 CA DMA 0 Control Register 51 40 INT4 Control Register 38 C8 DMA 0 Transfer Count Register 51 3E INT3 Control Regis...

Page 21: ...O space set 1 The peripheral control block PCB is located in memory space set 0 The PCB is located in I O space Bit 11 0 R19 R8 Relocation Address Bits The upper address bits of the PCB base address...

Page 22: ...rnal clock Bit 10 CBD CLKOUTB Drive Disable Set 1 Disable the CLKOUTB This pin will be three state Set 0 Enable the CLKOUTB Bit 9 CAF CLKOUTA Output Frequency selection Set 1 CLKOUTA output frequency...

Page 23: ...this pin should be held low for at least seven oscillator periods The Reset Status Figure shows the status of theRST pin and others relation pins WhenRST from low go high the state of input pin with w...

Page 24: ...the RST pin from low go high And the value of the reset configuration register provides the system information when software read this register This register is read only and the contents remain vali...

Page 25: ...d instruction fetch bus cycles I O read and I O write bus cycles use a separate I O address space Only IN OUT instruction can access I O address space and information must be transferred between the p...

Page 26: ...he internal chip select registers The R2 bit of UMCS offset 0A0h default is low so each one of the ARDY or SRDY should in ready state with pull high resistor when at power on reset or external reset T...

Page 27: ...ssor is in hold status HLDA is high the AO15 AO8 AD7 AD0 A19 A0 WR RD DEN 1 S 0 S 6 S BHE DT R and WB are floating and the UCS LCS 6 PCS 5 PCS 3 MCS 0 MCS and 3 PCS 0 PCS will be drive high After HOLD...

Page 28: ...nge without notice 28 CLKOUTA HOLD HLDA A19 A0 S6 S2 S0 AD7 AD0 RD WR DT R WLB ADDRESS 7 DATA DEN 6 BUS HOLD LEAVE WAVEFORM Case 1 Case 2 Ti Ti Ti Ti Ti T4 T1 T1 Floating Floating Floating Floating Fl...

Page 29: ...ct pin active region can be configured by the LB2 LB0 The default memory block size is from F0000h to FFFFFh LB2 LB1 LB0 Memory Block size Start address End Address 1 1 1 64k F0000h FFFFFh 1 1 0 128k...

Page 30: ...ss End Address 0 0 0 64k 00000h 0FFFFh 0 0 1 128k 00000h 1FFFFh 0 1 1 256k 00000h 3FFFFh 1 1 1 512k 00000h 7FFFFh Bit 11 8 Reserved Bit 7 DA Disable Address If the BHE ADEN pin is held high on the ris...

Page 31: ...S chip select block The bits 12 to 0 of the base address are always 0 The base address can be set to any integer multiple of the size of the memory block size selected in these bits For example if the...

Page 32: ...figured as peripheral chip select pins Set 0 PCS6 is configured as address bit A2 PCS5 is configured as A1 Bit 6 MS Memory or I O space Selector Set 1 The PCSx pins are active for memory bus cycle Set...

Page 33: ...e PCS0 Base Address Base Address FFh PCS1 Base Address 100h Base Address 1FFh PCS2 Base Address 200h Base Address 2FFh PCS3 Base Address 300h Base Address 3FFh PCS5 Base Address 500h Base Address 5FFh...

Page 34: ...The master mode has two connections Fully Nested Mode connection or Cascade Mode connection Interrupt Control Logic 0 0 0 1 1 1 Master Slave Mode Select FEH 14 Timer0 1 2 Interrupt REQ Timer0 REQ INT...

Page 35: ...pt are fixed Interrupt source Interrupt Type Vector Address EOI Type Priority Note Divide Error Exception 00h 00h 1 Trace interrupt 01h 04h 1 1 NMI 02h 08h 1 2 Breakpoint Interrupt 03h 0Ch 1 INTO Dete...

Page 36: ...errupt requests being serviced or pending If the interrupt is granted the interrupt controller uses the interrupt type to access a vector from the interrupt vector table If the external INT is active...

Page 37: ...2Ah 28h 22h 20h to define the interrupt controller operation Master Mode Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt source of the asynchronous serial port Serial Port Interrupt Control...

Page 38: ...trigger enable When this bit set to 1 and Bit 4 set to 0 interrupt is triggered by low go high edge The low go high edge will be latched one level till this interrupt is been serviced Bit 4 LTM Level...

Page 39: ...e as bit 2 0 of 44h Master Mode Bit 15 8 bit 6 5 Reserved Bit 7 ETM Edge trigger enable When this bit set to 1 and Bit 4 set to 0 interrupt is triggered by low go high edge The low go high edge will b...

Page 40: ...ow go high edge Bit 3 MSK Mask Set 1 Mask the interrupt source of the INT1 Set 0 Enable the INT1 interrupt Bit 2 0 PR Interrupt Priority These bits setting for priority selection is same as bit 2 0 of...

Page 41: ...le the INT0 interrupt Bit 2 0 PR Interrupt Priority These bits setting for priority selection is same as bit 2 0 of the register 44h Slave Mode Timer 1 Interrupt Control Register reset value is 0000h...

Page 42: ...0 PR Interrupt Priority These bits setting for priority selection is same as bit 2 0 of the register 44h Slave Mode reset value is 0000h Bit 15 4 Reserved Bit 3 MSK Mask Set 1 Mask the interrupt sour...

Page 43: ...Priority These bits setting for priority selection is same as bit 2 0 of the register 44h Master Mode Reset value un define Bit 15 DHLT DMA Halt Set 1 halts any DMA activity When non maskable interru...

Page 44: ...A Channel Interrupt Request Set 1 The corresponding DMA channel has an interrupt pending Bit 1 Reserved Bit 0 TMR Timer Interrupt Request Set 1 The timer control unit has an interrupt pending Slave Mo...

Page 45: ...rviced Bit 8 4 I4 I0 Interrupt In Service Set 1 the corresponding INT interrupt is currently being serviced Bit 3 2 D1 D0 DMA Channel Interrupt In Service Set 1 the corresponding DMA channel interrupt...

Page 46: ...Bit 2 0 PRM2 PRM0 Priority Field Mask Determining the minimum priority that is required in order for a maskable interrupt source to generate an interrupt Priority PR2 PR0 High 0 000 1 001 2 010 3 011...

Page 47: ...5 4 TMR2 TMR1 Timer 2 Timer1 Interrupt Mask The state of the mask bit of the Timer Interrupt Control register Set 1 Timer2 or Time1 has its interrupt requests masked Bit 3 2 D1 D0 DMA Channel Interrup...

Page 48: ...n the Poll register Bit 15 IREQ Interrupt Request Set 1 if an interrupt is pending The S4 S0 field contains valid data Bit 14 5 Reserved Bit 4 0 S4 S0 Poll Status Indicates the interrupt type of the h...

Page 49: ...Type The following interrupt type of slave mode can be programmed Timer 2 interrupt controller T4 T3 T2 T1 T0 1 0 1 b Timer 1 interrupt controller T4 T3 T2 T1 T0 1 0 0 b DMA 1 interrupt controller T4...

Page 50: ...r each data transfer DMA Operation Every DMA transfer consists of two bus cycles figure of Typical DMA Transfer and the two bus cycles can not be separated by a bus hold request a refresh request or a...

Page 51: ...A Control Registers Offset CAh DMA0 0 Reset Value FFF9h 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TC SINC SDEC DINC DDEC ST CHG Res TDRQ P SYN0 SYN1 INT DM IO B W SM IO DMA Transfer Count Register Offset C8...

Page 52: ...ing a DMA transfer when the source address is in memory space or I O space If the source address is in I O space 64Kbytes these bits must be programmed to 0000b Bit 15 0 DSA15 DSA0 Low DMA 0 Source Ad...

Page 53: ...it 10 SINC Source Increment Set 1 The Source address is automatically increment after each transfer Set 0 Disable the decrement function Bit 9 TC Terminal Count Set 1 The synchronized DMA transfer is...

Page 54: ...Address These bits are map to A19 A16 during a DMA transfer when the destination address is in memory space or I O space If the destination address is in I O space 64Kbytes these bits must be programm...

Page 55: ...fore the DMA cycle is initiated by the Bus Interface The DMA request is cleared four clocks before the end of the DMA cycle And no DMA acknowledge is provided since the chip selects MCSx PCSx can be p...

Page 56: ...nation device would not have time to deassert its DRQ signal CLKOUTA DRQ Case1 DRQ Case2 Fetch Cycle Fetch Cycle Source Synchronized Transfers T1 T2 T3 T4 T1 T2 T3 T4 NOTES Case1 Current source synchr...

Page 57: ...source These bits definition for timer 0 are same as the bits of register 5Eh for timer 1 Offset 50h 0 Reset Value 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Timer 0 Count Register TC15 TC0 Counter Element C...

Page 58: ...lective updating the EN bit The INH bit must be set 1 during writing the EN bit and both theINH bit and EN bit must be in the same write This bit is not stored and is always read as 0 Bit 13 INT Inter...

Page 59: ...timer1 count register increase one every four external clock Bit 3 P Prescaler Bit This bit and EXT 5Eh 2 define the timer 1 clock source The definition of setting the EXT P 0 0 Timer1 Count Register...

Page 60: ...ust be set 1 during writing the EN bit and the INH bit and EN bit must be in the same write Bit 14 INH Inhibit Bit This bit is allows selective updating the EN bit The INH bit must be set 1 during wri...

Page 61: ...he current count of timer 2 The count is incremented by one every four internal processor clocks Bit 15 0 TC15 TC0 Timer 2 Compare A Value Watchdog Timer Timer 1 can also be configure as a watchdog ti...

Page 62: ...0 4 1 0 1 5 1 1 0 6 1 1 1 7 Low Timer Counter Unit Output Mode Timers 0 and 1 can use one maximum count value or two maximum count value Timer 2 can use only one maximum count value Timer 0 and timer1...

Page 63: ...eserved Bit 11 TXIE Transmit Holding Register Empty Interrupt Enable This bit is set 1 to enable serial port to generates an interrupt request when the transmit holding register is empty Bit 9 LOOP Lo...

Page 64: ...t 0 One stop bit are used to signify the end of a frame Bit 2 TMODE Transmit Mode Set 1 Enable the transmit section of the serial port Set 0 Disable the transmit section of the serial port Bit 1 RSIE...

Page 65: ...hould be cleared by software Bit 1 PER Parity Error This bit is set to indicate that a party error occurred during reception of data and it will generate a serial pot interrupt request if the RISE bit...

Page 66: ...e Divisor The general formula for baud rate divisor is Baud Rate Microprocessor Clock 32 BAUDDIV 1 For example The Microprocessor clock is 22 1184MHz and the BAUDDIV 5 Decimal the baud rate of serial...

Page 67: ...s while the SSI is busy PB 1 Set 0 SDEN output is inactive Bit 1 DR TR Data Receive Transmit Complete Set 1 End of the transfer of data bit 7 SCLK rising edge during a transmit or receive operation Se...

Page 68: ...mit over the SDATA pin Synchronous Serial Transmit 0 Register The register contains data to be transfer from the processor to the peripheral on a write operation Bit 15 8 Reserved Bit 7 0 SD Send Data...

Page 69: ...e1 1 Write 12h 0 or 12h 1 DE0 0 or De1 0 Bit0 Bit7 Bit0 Bit7 Bit0 Bit7 Write to 14h or 16h PB 1 DR DT 0 PB 0 DR DT 1 PB 1 DR DT 0 PB 1 DR DT 0 PB 0 DR DT 1 PB 0 DR DT 1 Synchronous Serial Port Multipl...

Page 70: ...RDC RISC DSP Controller R8810LV RDC Semiconductor Co Rev 1 2 Subject to change without notice 70 DATA DATA CLKOUTA SDEN SCLK SDATA RX SDATA TX Synchronous Serial Interface Waveforms T1 T2 T3 T4...

Page 71: ...R Normal operation Input with 10k pull up 5 49 DEN Normal operation Input with 10k pull up 6 46 SRDY Normal operation Input with 10k pull down 7 22 A17 Normal operation Input with 10k pull up 8 20 A18...

Page 72: ...52 INT4 Input with 10k pull up 31 54 INT2 Input with 10k pull up Bit 15 0 PDATA31 PDATA16 PIO Data Bits These bits PDATA31 PDATA16 map to the PIO31 PIO16 which indicate the driven level when the PIO...

Page 73: ...Data Bus These bits PDATA15 PDATA0 map to the PIO15 PIO0 which indicate the driven level when the PIO pin as an output or reflects the external level when the PIO pin as an input Bit 15 0 PDIR 15 PDI...

Page 74: ...M6 M0 Refresh Base M6 M0 map to A19 A13 of the 20 bit memory refresh address Bit 8 0 Reserved Bit 15 9 Reserved Bit 8 0 RC8 RC0 Refresh Counter Reload Value Bit 15 E Enable RCU Set 1 Enable the refre...

Page 75: ...mod 000 r m 8 register 01011 reg 6 segment register 000 reg 111 reg 01 8 PUSHA Push all 01100000 36 POPA Pop all 01100001 44 XCHG Exchange register memory 1000011w mod reg r m 3 8 register with accumu...

Page 76: ...1 8 CMP Compare register memory with register 0011101w mod reg r m 1 7 register with register memory 0011100w mod reg r m 1 7 immediate with register memory 100000sw mod 111 r m data data if sw 01 1...

Page 77: ...byte word 1010010w 13 INS Input byte word from DX port 0110110w 13 OUTS Output byte word to DX port 0110111w 13 CMPS Compare byte word 1010011w 18 SCAS Scan byte word 101011w 13 LODS Load byte word t...

Page 78: ...ersegment 11111111 mod 101 r m mod 11 18 direct intersegment 11101010 segment offset 11 selector Iteration Control LOOP Loop CX times 11100010 disp 7 16 LOOPZ LOOPE Loop while zero equal 11100001 disp...

Page 79: ...for 16 bits operation need both 16 cycles 4 4 All jumps calls ret and loopXX instructions required to fetch the next instruction for the destination address Unconditional Fetch uOP will need 9 cycles...

Page 80: ...V GND Ground 0 0 0 V Vih Input High Voltage 1 2 0 Vcc 0 5 V Vih1 Input High Voltage RES 2 5 Vcc 0 5 V Vih2 Input High Voltage X1 2 5 Vcc 0 5 V Vil Input Low voltage 0 5 0 0 8 V Note 1 RST X1 pins not...

Page 81: ...ubject to change without notice 81 DC Electrical Characteristics Symbol Parameter Test condition Min Max Unit Note Icc Max Operating Current Vcc 3 6V 33MHz 85 mA Fmax Max operation clock frequency 5 3...

Page 82: ...2 Subject to change without notice 82 AC Characteristics CLKOUTA A19 A0 S6 AD15 AD0 ALE BHE DEN DTR UZI T1 T2 T3 T4 ADDRESS DATA UCS LCS S2 S0 TW STATUS READ CYCLE PCSx MCSX ADDRESS RD 2 1 3 4 5 6 7...

Page 83: ...ive 1 2T 10 ns 12 ALE width T 10 ns 13 RD active delay 0 15 ns 14 RD Pulse Width 2T 15 ns 15 RD inactive delay 0 20 ns 16 CLKOUTA HIGH to LCS UCS valid 0 20 ns 17 UCS LCS inactive delay 0 20 ns 18 PCS...

Page 84: ...1 2 Subject to change without notice 84 CLKOUTA A19 A0 S6 AD15 AD0 ALE WR BHE DEN DTR UZI T1 T2 T3 T4 ADDRESS DATA UCS LCS S2 S0 TW STATUS WRITE CYCLE PCSx MCSX ADDRESS WHB WLB 1 2 3 4 5 6 7 8 9 10 1...

Page 85: ...ALE inactive 1 2T 10 ns 11 WR active delay 0 15 ns 12 WR pulse width 2T 15 ns 13 WR inactive delay 0 15 ns 14 WHB WLB active delay 0 20 ns 15 WHB WLB inactive delay 0 20 ns 16 BHE active delay 0 20 ns...

Page 86: ...source synchronized transfer is not followed immediately by another DMA transfer No Description MIN MAX Unit 1 DRQ is confirmed time 0 10 ns CLKOUTA A19 A0 AD15 AD0 ALE RD WR WLB WHB UCS S2 S0 S6 DRQ0...

Page 87: ...ransfer is followed immediately by another DMA transfer No Description MIN MAX Unit 1 DRQ is confirmed time 0 3 ns CLKOUTA A19 A0 AD15 AD0 ALE RD WR WLB WHB UCS S2 S0 S6 DRQ0 DMA 2 c0000 C0002 20002 0...

Page 88: ...nit 1 HOLD setup time 0 10 ns 2 HLDA Valid Delay 0 20 ns 3 HOLD hold time 0 3 ns 4 HLDA Valid Delay 0 20 ns CLKOUTA A19 A0 AD15 AD0 ALE RD WR WLB UCS S2 S0 HLDA HOLD HLDA Timing ffff4 zZZZZ f0 4 DEN f...

Page 89: ...conductor Co Rev 1 2 Subject to change without notice 89 No Description MIN MAX Unit 1 ARDY Resolution Transition setup time 0 10 ns 2 ARDY active hold time 0 10 ns CLKOUTA ALE ARDY SRDY ARDY Timing L...

Page 90: ...C Semiconductor Co Rev 1 2 Subject to change without notice 90 No Description MIN MAX Unit 1 SRDY transition setup time 0 10 ns 2 SRDY transition hold time 0 3 ns CLKOUTA ALE ARDY SRDY SRDY Timing LCS...

Page 91: ...91 PACKAGE INFORMATION PQFP 0 089 c SEATING PLANE 0 25 MIN A1 0 22 0 38 b1 b 0 22 0 30 0 33 0 13 0 23 0 13 0 17 c1 c WITH PLATING BASE METAL A D1 20 00 0 10 D 23 20 0 25 E1 14 00 0 10 E 17 20 0 25 A 0...

Page 92: ...Rev 1 2 Subject to change without notice 92 LQFP Sealing Plane 1 25 26 50 51 75 76 100 0 127 TYP A 0 076 MAX 0 50 TYP 1 60 MAX 1 00 REF 0 2S TYP GAUGE PLANE 16 00 0 10 14 00 0 10 16 00 0 10 14 00 0 10...

Page 93: ...LV RDC Semiconductor Co Rev 1 2 Subject to change without notice 93 Revision History Rev Date History 1 0 2001 4 30 Formal release 1 1 2001 6 19 Address and Phone number update 1 2 2001 8 15 Modify Wa...

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