Racal Instruments 3152, User Manual

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SCPI Command Reference 4-19
Service Request
Enable
Register (SRE)
The Service Request enable register is an 8-bit register that enables
corresponding summary messages in the Status Byte Register.
Thus, the application programmer can select reasons for the
synthesizer to issue a service request by altering the contents of the
Service Request Enable Register.
The Service Request Enable Register is read with the *SRE?
common query. The response to this query is a number that
represents the sum of the binary-weighted value of the Service
Request Enable Register. The value of the unused bit 6 is always
zero.
The Service Request Enable Register is written using the *SRE
command followed by a decimal value representing the bit values
of the Register. A bit value of 1 indicates an enabled condition.
Consequently, a bit value of zero indicates a disabled condition. The
Service Request Enable Register is cleared by sending *SRE0. The
synthesizer always ignores the value of bit 6. Summary of *SRE
commands is given in the following.
*SRE0 - Clears all bits in the register.
*SRE1 - Not used.
*SRE2 - Not used.
*SRE4 - Not used.
*SRE8 - Not used.
*SRE16 - Service request on MAV.
*SRE32 - Service request on ESB summary bit.
*SRE128 - Not used.
Standard Event
Status Register (ESR)
The Standard Event Status Register reports status for special
applications. The 8 bits of the ESR have been defined by the IEEE-
STD-488.2 as specific conditions which can be monitored and
reported back to the user upon request. The Standard Event Status
Register is destructively read with the *ESR? common query. The
Standard Event Status Register is cleared with a *CLS common
command, with a power-on and when read by *ESR?.
The arrangement of the various bits within the register is firm and
is required by all GPIB instruments that implement the IEEE-STD-
488.2. Description of the various bits is given in the following:
Bit 0 - Operation Complete. Generated in response to the *OPC
command. It indicates that the device has completed all selected
and pending operations and is ready for a new command.
Bit 1 - Request Control. This bit operation is disabled on the Model
3152.
Bit 2 - Query Error. This bit indicates that an attempt is being made
to read data from the output queue when no output is either present
or pending.