The gate bias voltage is provided by trimmer potentiometer R5, which is supplied by a 5V 78L05
voltage regulator (TO92 package) IC1, not shown in this schematic fragment. The bias voltage is
supplied only during transmit (via P-channel MOSFET Q4, which is ON during transmit only).
A much more frequently seen bias arrangement has two separate trimmer potentiometers, to
adjust the bias voltage to each transistor individually. The theory behind this is that the transistor’s
Gate-Source Threshold Voltage varies from device to device, so needs to be set individually per
device. The Vishay IRF510 datasheet for example, specifies V
GS
minimum 2.0V, maximum 4.0V.
Quite a wide range.
It is instructive to compare this schematic to the schematic of the PA section for the QRP Labs
10W Linear kit
(that amplifier is designed for 160m to 10m operation)
and discuss the differences in gate bias arrangements.
The same DC power method is used (here bifilar transformer T203) and the same output
combiner/impedance matching transformer T204.
Note the negative feedback network between the transistor drains and gates (for example, in the
case of Q207, the series inductor-resistor-capacitor consisting of L204, R216 and C209). This
helps to provide stability at all operating frequencies, improves linearity and also flattens the gain
across a wide frequency range (this amplifier is designed for 160m to 10m operation).
In the case of this 50W amplifier (refer back to the schematic), it is intended for single band
operation only, and I don’t care about linearity (it is a Class-C amplifier for CW), neither do I care
about gain flatness across the whole of HF from 2 to 30MHz. The amplifier is intended for 40, 30
or 20m operation and I just want as much power output as possible! So the feedback components
are deleted; naturally this also saves cost and board space.
50W QCX PA kit assembly
1.00q
45
