Princeton Instruments PI-MAX 3 System, Manual, Page: 44 / 150

44 PI-MAX
®
3 System Manual Version 1.A
Limitations of hardware binning include:

Lowered resolution because charge from adjacent pixels is summed into a super
pixel.

Increased possibility to blooming. Because shift register pixels typically hold only
twice as much charge as image pixels, the binning of large sections may result in
saturation and spilling of charge back into the image area

Possible data loss if the total charge binned together exceeds the capacity of the
shift register or output node.

For dual port operation, there are symmetry requirements that limit the choice of
patterns. Regions of interest (ROIs) must be symmetrical about the center line
(horizontal).

The number of pixels in the serial (horizontal) direction must be evenly divisible
by 4, even after binning.
The possibility of blooming or data loss strongly limits the number of pixels that may be
binned in cases where there is a small signal superimposed on a large background, such
as signals with a large fluorescence. Ideally, one would like to bin many pixels to
increase the S/N ratio of the weak peaks but this cannot be done because the fluorescence
would quickly saturate the CCD. The solution is to perform the binning in software.
Limited hardware binning may be used when reading out the CCD. Additional post-
processing binning is accomplished in software, producing a result that represents many
more photons than was possible using hardware binning.
CCD Type and Readout Port(s)
The PI-MAX3 will either have a full frame or an interline CCD. Full frame CCDs such as
the 1024x256 device have a single port for readout. The 1024x1024 interline CCD is
designed for either dual or single port readout. Dual port readout is about two times faster
than single port readout and occurs whenever the full frame is being read out or when an
ROI is symmetrical about the center of the CCD. Single port readout will automatically
occur when an ROI is not symmetrical about the center of the CCD. The single port used
is determined at the factory.
Full Frame Binning
Figure 12 shows an example of 2

2 binning with dual port operation for an interline
array. Each pixel of the image displayed by the software represents 4 pixels of the array.
Figure 13 shows an example of single port operation for a full frame array.