PLX Technology PEX 8311RDK, Hardware Reference Manual

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PEX 8311RDK Hardware Reference Manual, Version 0.90
20 © 2005 PLX Technology, Inc. All rights reserved.
4.4.2 Uncommitted FPGA footprint
The footprint FP2 has been designed to accept either a 100 pin Altera Cyclone FPGA such as the
EP1C3T144 or a 100 pin Xilinx Spartan-3E FPGA. Although care has been taken to ensure that the
configurable resistor options and connections comply with these devices it is recommended that the user
carefully checks the latest documentation from the FPGA manufacturer in case of product changes
subsequent to the publication of this document.
In addition to the devices noted above other parts may also be assembled onto FP2. However, it is up to
the user to determine the appropriate connections between the device and the PEX 8311 local bus.
It should be noted that PLX does not provide FPGA code examples. Section 7 - CPLD Verilog Code –
details the code which is used in the on board CPLD and this may be used as a guide.
4.4.2.1 Uncommitted FPGA connections
The following modules can be used in conjunction with the uncommitted FPGA footprint:
• Unpopulated configuration Resistors
• Configuration PROM
•
JTAG headers
•
User VCC
• Through hole pads
Depending on the application one or more of these can be used to interconnect the FPGA to the existing
circuitry on the PEX 8311 RDK, to set up FPGA configuration and/or to link to other uncommitted
elements on the FPGA
4.4.2.2 Uncommitted FPGA to PEX 8311 local bus
The uncommitted FPGA can be connected to the PEX 8311 local bus in two ways:
a) Using the resistor options
b) Wiring between the through hole pads (PF1 to PF144) and the test headers (LAH1 to LAH6)
Any combination of the above can be used.
Table 4-4 shows the resistor options used to connect the Altera Cyclone or the Xilinx Spartan-3E arrays
to the PEX 8311 local bus.