PLX Technology PEX 8311RDK, Hardware Reference Manual

Page: 29 / 66

PEX 8311RDK Hardware Reference Manual, Version 0.90
© 2005 PLX Technology, Inc. All rights reserved.
21
Table 4-4. Uncommitted FPGA resistor configuration
FPGA
Pin No.
Xilinx Pin
Name
Altera Pin
Name
Local
Signal
Bus
No.
Xilinx link
resistor
Xilinx
Voltage R
Xilinx
Capacitor
Altera link
resistor
Altera
Voltage R
Altera
Capacitor
1 PROG_B INIT_DONENote 1 A1 180 User IO
2 I/O I/O LD0 A2 182 182
3 I/O I/O LD1 A3 186 186
4 I/O I/O LD2 A4 191 191
5 I/O I/O LD3 A5 196 196
6 IP I/O LBG1 A6 198 198
7 I/O I/O LD4 A7 200 200
8 I/O 3.3V LA2_X A8 203 176 102
9 1.2V GND A9 209 190 103 209 195
10 IP I/O BREQo A10 214 214
11 GND I/O LA2_A A11 220 262 219
12 IP I/O (nCS0) LA20 A12 225 225
13 3.3V DATA0 USERo A13 231 201 104 Note 2
14 I/O nCONFIG GPIO0 A14 User IO 234
15 I/O 1.5V LA4_X A15 237 239 210 104
16 I/O CLK0 LCLK_T A16 User IO 241
17 I/O CLK1 LA5_X A17 244 NC
18 IP GND A18 User IP 249 235
19 GND GND A19 178 235 178 235
20 I/O nCEO USERi A20 User IO Note 2
21 I/O nCE LA6_X A21 183 Note 2
22 I/O MSEL0 LA7_X A22 187 Note 2
23 I/O MSEL1 LA8_X A23 192 Note 2
24 IP DCLK GPIO1 A24 User IP Note 2
25 I/O I/O LD5 A25 199 199
26 I/O I/O LD6 A26 202 202
27 GND I/O LA4_A A27 207 265 205
28 3.3V I/O LA5_A A28 212 267 112 211
29 IP 3.3V LA21_X A29 216 218 251 107
30 2.5V GND A30 224 256 107 223 272
31 I/O I/O LD7 A31 228 228
32 I/O I/O LD8 A32 233 233
33 I/O I/O LD9 A33 236 236
34 I/O I/O LD10 A34 240 240
35 I/O I/O LD11 A35 242 242
36 IP I/O LINTo# A36 246 246
37 GND I/O LA6_A B1 278 275 277
38 IP I/O LSERR# B2 282 282
39 I/O I/O LD12 B3 287 287
40 INIT_B I/O Note 1 B4 292 User IO
41 IP I/O CS_3# B5 294 294
42 3.3V I/O LA7_A B6 300 281 115 298
43 I/O GND LA9_X B7 305 307 291
44 I/O 3.3V LA10_X B8 312 313 354 123
45 1.2V GND B9 320 311 116 320 318
46 GND 1.5V B10 323 380 323 374 124
47 IP I/O LA16 B11 328 328
48 IP I/O LA17 B12 333 333
49 3.3V I/O LA8_A B13 327 117 336
50 I/O I/O LD15 B14 338 338