PLX Technology PEX 8311RDK Hardware Reference Manual Download

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LBE#0
LBE#1
LBE#2
LBE#3

LA3

LA29

LA10

LA13

LA8
LA9

LA11

LA25
LA26

LA2

LA24

LA30

LA6
LA7

LA19

LA5

LA12

LA21

LA27
LA28

LA31

LA4

LA23

LA15

LA17
LA18

LA22

LA20

LA14

LA16

LBE#0

LBE#2

LA2

LA4

LA6

LA8

LA10

LA12

LA13
LA11

LA9
LA7
LA5
LA3

LBE#3
LBE#1

LA25

LA21

LA16

LA29

LA19

LA28

LA23

LA26

LA15

LA20

LA24

LA18

LA27

LA22

LA14

LA17

LD5

LD1

DP0

LD9

DP3

LD8

LD3

LD6

LA31

LD0

LD4

DP2

LD7

LD2

LA30

DP1

DP0
DP1
DP2
DP3

LD24
LD22
LD20
LD18
LD16
LD14
LD12
LD10

LD11

LD13

LD15

LD17

LD19

LD21

LD23

LD25

LD31

LD27

BTERM#

LD28

BLAST#

LD29

LD30

LHOLDA

LHOLD

ADS#

LW/R#

WAIT#

LD26

READY#

DREQ0#

DACK0#

LD23

LD20

LD3

LD29

LD24

LD26

LD30

LD13

LD27

LD0

LD17

LD14

LD31

LD21

LD18

LD28

LD15

LD1

LD25

LD22

LD12

LD2

LD19

LD16

LD9

LD4

LD6

LD10

LD7

LD11

LD8

LD5

USERi/LLOCKi#
USERo/LLOCKo#

DREQ1#

DACK1#

GPIO0

PMEIN#
PMEOUT#
WAKEIN#

GPIO2

GPIO1

GPIO3

BAR0ENB#

BREQi

BREQo

BIGENDE#

DMPAF/EOT#

LINTo#
LINTi#

LSERR#

LRESET#

3.3VCC

2.5VCC

PCIE12VCC

PCIE3.3VCC

LA[31:2]

3,4,6,9,10,11,12

LBE#[3:0]

3,4,6,12

LD[31:0]

3,4,6,9,10,11,12

DP[3:0]

3,11

LCLK_T

3,9,12

LW/R#

3,4,6,12

READY#

3,4,6,12

ADS#

3,4,6,11

LHOLD

3,4

BTERM#

3,4,6,11

WAIT#

3,6,12

BLAST#

3,4,6,11

LHOLDA

3,4

GPIO0

2,9,10

GPIO1

2,9,10

DACK0#

3,4,6,10

DREQ0#

3,4,6,11

GPIO2

2,10,11

GPIO3

2,9,11

DACK1#

3,4,6,11

DREQ1#

3,4,6,12

WAKEIN#

BAR0ENB#

USERi/LLOCKi#

3,6,9,10

USERo/LLOCKo#

3,6,9

PMEIN#

3,11,12

PMEOUT#

BREQi

3,6,9,11

BREQo

3,6,9,11

BIGEND#

3,11

DMPAF/EOT#

3,4,6,11

LINTi#

3,6,12

LINTo#

3,6,9

LSERR#

3,10

LRESET#

3,6,12

Title

Size

Document Number

Rev

Date:

Sheet

000

Test Headers

PLX TECHNOLOGY, INC.

870 Maude Ave, Sunnyvale, CA 94085

Custom

Wednesday, December 14, 2005

www.plxtech.com

Title

Size

Document Number

Rev

Date:

Sheet

000

Test Headers

PLX TECHNOLOGY, INC.

870 Maude Ave, Sunnyvale, CA 94085

Custom

Wednesday, December 14, 2005

www.plxtech.com

Title

Size

Document Number

Rev

Date:

Sheet

000

Test Headers

PLX TECHNOLOGY, INC.

870 Maude Ave, Sunnyvale, CA 94085

Custom

Wednesday, December 14, 2005

www.plxtech.com

91-0058-000-A

TP3

R120

0_NP

R120

0_NP

TP11

R121

0_NP

R121

0_NP

TP9

R114

0_NP

R114

0_NP

R115

0_NP

R115

0_NP

R127
100

+5V

D16

D14

D12

D10

D17

D15

D13

D11

GND

LAH1

Logic Analyzer Header

LAH1

Logic Analyzer Header

TP5

R122

+5V

D16

D14

D12

D10

D17

D15

D13

D11

GND

LAH5

Logic Analyzer Header

LAH5

Logic Analyzer Header

R124
1.2K

TP4

TP10

+5V

D16

D14

D12

D10

D17

D15

D13

D11

GND

LAH6

Logic Analyzer Header

LAH6

Logic Analyzer Header

R116

0_NP

R116

0_NP

+5V

D16

D14

D12

D10

D17

D15

D13

D11

GND

LAH4

Logic Analyzer Header

LAH4

Logic Analyzer Header

R117

0_NP

R117

0_NP

TP7

+5V

D16

D14

D12

D10

D17

D15

D13

D11

GND

LAH3

Logic Analyzer Header

LAH3

Logic Analyzer Header

LED8

LED

LED8

LED

LED6

LED

LED6

LED

+5V

D16

D14

D12

D10

D17

D15

D13

D11

GND

LAH2

Logic Analyzer Header

LAH2

Logic Analyzer Header

LED5

LED

LED5

LED

R118

0_NP

R118

0_NP

TP6

R125
330

TP8

R119

0_NP

R119

0_NP

R123

Summary of Contents for PEX 8311RDK

Page 1: ...PEX 8311RDK Hardware Reference Manual...

Page 2: ......

Page 3: ...PEX 8311RDK Hardware Reference Manual Version 0 90 December 2005 Website http www plxtech com Support http www plxtech com support Phone 408 774 9060 800 759 3735 Fax 408 774 2169...

Page 4: ...s to this publication known as errata PLX assumes no liability whatsoever including infringement of any patent or copyright for sale and use of PLX products PLX Technology and the PLX logo are registe...

Page 5: ...oint Root Complex operation 13 4 Mechanical Architecture 15 4 1 Monitoring Points Test headers Indicators Control and DIP Switch Summary 16 4 1 1 Monitoring Points 16 4 1 2 Headers 16 4 1 2 1 Test Hea...

Page 6: ...r Local Bus Memory Map 10 Table 3 4 PEX 8311RDK LED Indicators 11 Table 3 5 PEX 8311RDK Power supply currents 12 Table 3 6 PEX 8311RDK Power jumper and resistor options 12 Table 4 1 PEX 8311RDK Defaul...

Page 7: ...hout notice Although every effort has been made to ensure the accuracy of this manual PLX shall not be liable for any errors incidental or consequential damages in connection with the furnishing perfo...

Page 8: ......

Page 9: ...bus J mode applications The RDK provides 5 surface mount QFP SOIC SSOP footprints and for hardware designers to easily add processors DSPs ASICs FPGAs memory and I O devices to test simulate and debu...

Page 10: ...ace 8 KB general purpose shared RAM 1 2 PEX 8311RDK Features PLX PCI Express to PCI bridge device in a 21 x 21 mm 337 ball PBGA package Single x1 PCI Express Edge connector for insertion into standard...

Page 11: ...between a PCI Express base board and local bus processors or logic The PEX 8311RDK is designed to showcase many of the PEX 8311 features when operating in Endpoint mode The PEX 8311RDK s form factor...

Page 12: ...l Clock Figure 3 1 PEX 8311RDK Hardware Architecture 3 1 PEX 8311 PCI Express Bridge Device The PEX 8311 U1 is a high performance PCI Express to local bus device that enables designers to migrate lega...

Page 13: ...Hz and can directly interface with the PEX 8311 The Atmel AT25640 device as used in the PEX 8311RDK is recommended Other compatible 128 byte serial EEPROM s include the Atmel AT25010A Catalyst CAT25C0...

Page 14: ...7 0 22h 8500 Local Miscellaneous Control Register 1 Processor Local Bus Big Little Endian Descriptor Register LMISC1 7 0 BIGEND 7 0 24h 0000 MSW of Range for PCI to Local Expansion ROM EROMRR 31 16 26...

Page 15: ...R Bridge Support Extensions the LSB is reserved PMDATA 7 0 PMCSR_BSE 7 0 62h 0000 Power Management Control Status Bits 15 7 2 and 1 0 are reserved PMCSR 15 0 3 3 Local and PCI Express Hardware Element...

Page 16: ...resses to the SBSRAM The SBSRAM controller also generates the active low ready signal READY to terminate normal PEX 8311 memory cycles and also generates the active low BTERM input to the PEX 8311 to...

Page 17: ...Configuration for details on re configuring the RDK hardware for J Mode operation It can be used for expansion and prototyping Both either a master and or slave devices may be connected to this conne...

Page 18: ...k PCI Express RefClk enters the PEX 8311RDK through the PCI Express card edge male connector RefClk is laid out as a 100 Ohm controlled impedance microstrip differential pair Trace length mismatch is...

Page 19: ...r Indication LED8 2 5V power is on GPIO0 LED1 Output OFF 0 Link Down ON 1 Link Up GPIO1 LED2 ON GPIO1 Input by default GPIO2 LED3 ON GPIO2 Input by default GPIO3 LED4 ON GPIO3 Input by default 3 6 PEX...

Page 20: ...ns Various power jumpers and resistor options are available on the PEX 8311 RDK to allow the power consumption of the PEX 8311 to be measured under different operating conditions Table 3 6 details the...

Page 21: ...nt Mode 3 7 1 Wakeup The PEX 8311 asserts the WAKEOUT signal or sends a PCI Express beacon for the following PMEIN pin is asserted while link is in L2 state PCI Express beacon is received while link i...

Page 22: ...12V to the 3 3V regulator U4 by removing R21 and populating R22 with a 0 ohm jumper The PCIE3 3VCC can then be provided by U4 by populating R27 with a 0 ohm jumper Extreme care must be taken to ensur...

Page 23: ...n the PCI Express CEM specification The board is an eight layer 6 6 L x 8 15 W PC board The board height is greater than that noted in the PCI Express CEM specification and care must be taken to ensur...

Page 24: ...ng or prototype area extension All PEX 8311 Local Bus signals configuration and status signals are well arranged within these headers Headers LAH2 and LAH3 contain Local Bus address signals Headers LA...

Page 25: ...closed JP2 OPEN GPIO0 drives LED1 JP3 1 2 Pull GPIO1 high JP4 1 2 Pull GPIO2 high JP5 1 2 Pull GPIO3 high J7 CLOSED 3 3V supply to PEX 8311 J8 CLOSED 1 5V supply to PEX 8311 J9 CLOSED 2 5V supply to P...

Page 26: ...5 Ohms 10 single ended impedance and 100 Ohms 5 differential Figure 4 3 details the layers used in the PCB manufactuer The thickness of the various layers is detailed in Table 4 2 Layer thickness SOLD...

Page 27: ...shroud themselves PLX takes no responsibility for boards damaged during this operation 4 4 Prototyping Area The RDK board contains a small prototyping area with various surface mount footprints and a...

Page 28: ...does not provide FPGA code examples Section 7 CPLD Verilog Code details the code which is used in the on board CPLD and this may be used as a guide 4 4 2 1 Uncommitted FPGA connections The following m...

Page 29: ...244 NC 18 IP GND A18 User IP 249 235 19 GND GND A19 178 235 178 235 20 I O nCEO USERi A20 User IO Note 2 21 I O nCE LA6_X A21 183 Note 2 22 I O MSEL0 LA7_X A22 187 Note 2 23 I O MSEL1 LA8_X A23 192 No...

Page 30: ...69 IP I O DACK0 B33 339 339 70 I O I O LD28 B34 342 342 71 CCLK I O Note 1 B35 345 User IO 72 DONE I O Note 1 B36 347 User IO 73 GND I O LA11_A C1 387 384 386 74 I O I O LD29 C2 391 391 75 I O I O LD3...

Page 31: ...LK8 I O LCLK_T D20 496 User IO 129 IP I O D21 User IP User IO 130 I O I O LW R D22 505 505 131 I O I O LD14 D23 508 508 132 I O I O READY D24 511 511 133 GND I O LA28_A D25 518 615 516 134 I O I O WAI...

Page 32: ...e uncommitted FPGA There are three methods of programming or configuring the uncommitted FPGA a Program through the JTAG interface b Program using the PEX 8311 GPIO c Program using the Configuration P...

Page 33: ...in header R197 0 DCLK 24 5 7 JP3 2 3 Notes 1 This pin is connected to TP20 Connect this pin to the same supply voltage as the download cable 2 For some programmers it may be necessary to tie this pin...

Page 34: ...GA signal pin Pull up resistor or jumper Pull down resistor or jumper JP7 2 Vref 2 5V JP7 4 F_TMS R172 100 1 TMS 108 JP7 6 F_TCK R170 100 1 TCK 110 JP7 8 F_TDO R171 0 1 TDO 109 JP7 10 F_TDI R173 100 1...

Page 35: ...4 and add R264 3 GPIO1 must be configured to be an output In addition to the above resistors the appropriate power supply and ground resistors must also be populated Table 4 8 shows the resistor optio...

Page 36: ...Configuration PROMs FP1 is designed to accept the VO20 VOG20 packaged versions of the XCFxxS platform flash PROMs Table 4 9 details the resistor configurations required to interface a platform flash...

Page 37: ...programming mode or resetting the device 3 R348 and R353 are only required if BitGen option DriveDONE No see the appropriate Xilinx data sheet for more details Ideally pin 3 or pin 6 of RN10 should be...

Page 38: ...n C mode using a 32 bit data bus In addition every feature of the PEX 8311 is connected to the FPGA For some applications more FPGA I O will be required for user circuitry attached to the FPGA There a...

Page 39: ...o X means removed Table 5 1 RDK Board Mode Configuration Resistors Value C Mode Default J Mode Mode Pins Configuration R32 1 10w 10K ohm 5 X R33 1 10w 10K ohm 5 R34 1 10w 0 ohm 5 X R35 1 10w 0 ohm 5 X...

Page 40: ......

Page 41: ...in the PC s main memory For example assume the HBuf has physical address starting at 01F80000h b Enter 8 long words of test data to the SBSRAM For example el s0 11111111 el s0 4 22222222 el s0 8 3333...

Page 42: ...ogy Inc All rights reserved h Change the direction of the DMA transfer to PCI to Local for DMA CH0 by modifying the Descriptor Pointer 90h value from 8 to 0 i Click the Start Transfer button to perfor...

Page 43: ...mcsn sramoen lholda lbg sram_adds sram_bwn csn input clk adsn blastn lwdrdn lhold input 1 0 lbr input 3 0 lben input 9 2 adds_in input 31 28 adds_4msb output readyn btermn sramcsn sramoen lholda outpu...

Page 44: ...s posedge clk if adsn adds_4msb 4 b0000 a31_28 3 0 adds_4msb 31 28 SRAM control state machine parameter s0 2 b00 s1 2 b01 s2 2 b10 s3 2 b11 always posedge clk casex state s0 begin sramoen 1 oeb b1 if...

Page 45: ...moen 1 sramcsn 0 oer b0 oeb b1 state s1 end end else begin sram_adds 9 2 sram_adds 9 2 1 sramoen 0 sramcsn 0 oer b0 oeb b1 state s2 end s2 if lwdrdn blastn begin sramoen 1 sramcsn 1 oer b1 oeb b1 stat...

Page 46: ...LX Technology Inc All rights reserved sramcsn 1 oer b1 oeb b1 state s0 end default state s0 endcase always posedge clk begin if lhold lholda lhold else lholda 0 if lhold lbr 1 lbg 1 lbr 1 else lbg 1 0...

Page 47: ...vale CA 94085 USA Tel 408 774 9060 Tel 800 759 3735 Fax 408 774 2169 http www plxtech com PEX 8311 Data Book Version xx or higher PEX 8311RDK Hardware Reference Manual PCI Special Interest Group PCI S...

Page 48: ......

Page 49: ...21VRC TR8 LED SMT Red 0805 LED1 LED2 LED3 LED4 10 3 Chicago CMD17 21VGC TR8 LED SMT Green 0805 LED5 LED6 LED8 11 1 Steward L10805E400R Ferrite chip 47 uH 500mA 0805 L1 12 1 CTS Corp 742C083271JTR Resi...

Page 50: ...U10 31 1 Samsung K7B403625B IC Synchronous SRAM 4 Mbit 128Kx36 Flow Through TQFP 100 pins 14x20 mm U11 THROUGH HOLE COMPONENTS 32 4 Molex 22 28 4020 Header 2 x 1 pins 0 1 vert no shroud Thru Hole JP1...

Page 51: ...k EP1345HSPD 66 666M 54 1 Mil Max 110 93 308 41 001 Socket 8 pin dip 0 3 solder tail low profile Thru Hole U13 55 1 Panasonic ERJ3GEYJ100V Resistor 10 ohms 5 0 1 W 0603 R136 NIC Components NRC06J100TR...

Page 52: ...ithout notice Products may have minor variations to this publication known as errata PLX assumes no liability whatsoever including infringement of any patent or copyright for sale and use of PLX produ...

Page 53: ...e 1 2 C15 0 1uF C15 0 1uF 1 2 3 JP3 JP3 C34 10uF C34 10uF WAKEIN B2 ROOT_COMPLEX A18 PLXT2 A10 EERDDATA M3 TEST N1 BUNRI F3 BTON D10 SMC V4 TMC E2 TMC1 V3 TMC2 E3 TDI A14 TCK A13 TMS A11 TRST B14 WAKE...

Page 54: ...5 6 7 8 RN2 742 08 3 103 J XX RN2 742 08 3 103 J XX C45 0 1uF C45 0 1uF R34 0 R34 0 R41 1K R41 1K C59 0 1uF C59 0 1uF R45 10K R45 10K R33 10K_NP R33 10K_NP 1 2 3 4 5 6 7 8 RN6 742 08 3 103 J XX RN6 7...

Page 55: ...PA56 PA56 PA12 PA12 PA31 PA31 C87 0 1uF C87 0 1uF R108 0 R108 0 C89 0 01uF C89 0 01uF PA50 PA50 PA6 PA6 PA17 PA17 PA39 PA39 R74 0 R74 0 R92 10K R92 10K SA0 37 SA1 36 DQa0 52 DQa1 53 DQa2 56 DQa3 57 D...

Page 56: ...Size Document Number Rev Date Sheet of 000 Test Headers PLX TECHNOLOGY INC 870 Maude Ave Sunnyvale CA 94085 Custom 5 15 Wednesday December 14 2005 www plxtech com Title Size Document Number Rev Date S...

Page 57: ...stom 6 15 Wednesday December 14 2005 www plxtech com Title Size Document Number Rev Date Sheet of 000 PLX Option Module Connector PLX TECHNOLOGY INC 870 Maude Ave Sunnyvale CA 94085 Custom 6 15 Wednes...

Page 58: ...ND 38 RX6 40 RX6 42 GND 44 RX7 46 RX7 48 GND 5 TX1 7 TX1 9 GND 11 TX2 13 TX2 15 GND 17 TX3 19 TX3 21 GND 23 TX4 25 TX4 27 GND 29 TX5 31 TX5 33 GND 35 TX6 37 TX6 39 GND 41 TX7 43 TX7 45 GND 47 J5 Midbu...

Page 59: ...12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 FP1 20 pin SSOP 0 025 pitch FP1 20 pin SSOP 0 025 pitch PA74 PA74 R167 0_NP R167 0_NP PA78 PA78 R163 0_NP R163 0_NP R156 0_NP R156 0_NP C101 0 01...

Page 60: ...266 0_NP R266 0_NP C112 10nF_NP C112 10nF_NP R180 56_NP R180 56_NP R233 0_NP R233 0_NP R187 0_NP R187 0_NP R272 0_NP R272 0_NP R246 0_NP R246 0_NP R217 0_NP R217 0_NP C106 10nF_NP C106 10nF_NP R201 0_...

Page 61: ...57 0_NP R357 0_NP R343 0_NP R343 0_NP R375 0_NP R375 0_NP R273 0_NP R273 0_NP R292 0_NP R292 0_NP R376 0_NP R376 0_NP R365 0_NP R365 0_NP R296 0_NP R296 0_NP R315 0_NP R315 0_NP R350 0_NP R350 0_NP C1...

Page 62: ...0_NP R461 0_NP R461 0_NP R392 0_NP R392 0_NP R418 0_NP R418 0_NP R422 0_NP R422 0_NP R381 0_NP R381 0_NP R389 0_NP R389 0_NP R438 0_NP R438 0_NP R439 0_NP R439 0_NP R478 0_NP R478 0_NP R454 0_NP R454...

Page 63: ...F_NP C148 10nF_NP C141 10nF_NP C141 10nF_NP R535 0_NP R535 0_NP R534 0_NP R534 0_NP R489 0_NP R489 0_NP R609 0_NP R609 0_NP R550 0_NP R550 0_NP R569 0_NP R569 0_NP R617 0_NP R617 0_NP R501 0_NP R501 0...

Page 64: ...PF117 PF132 PF132 PF7 PF7 PF42 PF42 PF76 PF76 PF120 PF120 PF33 PF33 PF68 PF68 PF102 PF102 PF10 PF10 PF45 PF45 PF80 PF80 PF124 PF124 PF20 PF20 PF72 PF72 PF106 PF106 PF107 PF107 PF127 PF127 PF48 PF48 P...

Page 65: ...F180 PF155 PF155 PF152 PF152 PF218 PF218 PF176 PF176 PF205 PF205 PF230 PF230 PF245 PF245 PF177 PF177 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20...

Page 66: ...15 15 Wednesday December 14 2005 91 0058 000 A N C T1 N C P1 N C W6 N C B12 N C B11 N C C11 N C B13 N C C8 N C B7 N C B9 N C R2 N C N3 N C M2 N C P3 N C V8 N C N2 N C T2 N C P2 N C N4 N C V7 N C R1 N...

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