PLX Technology PEX 8311RDK, Hardware Reference Manual

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PEX 8311RDK Hardware Reference Manual, Version 0.90
8 © 2005 PLX Technology, Inc. All rights reserved.
3.3.1 Local Clock
The PEX 8311 has a local clock input which is required for normal operation. The Cypress Semiconductor
CY2305 Zero Delay 1-to-5 clock buffer (U7) provides onboard local clock distribution to the PEX 8311,
SBSRAM, CPLD, test headers and the POM connector. The CY2305 input is sourced by the socketed
onboard oscillator (U8). The socketed oscillator (U8) can be changed to allow PEX 8311 local bus
operation at any frequency from 10 to 66MHz. The 10MHz minimum is a restriction of the CY2305, the
local bus of the PEX 8311 can run at any frequency from 0 to 66MHz.
3.3.2 Synchronous Burst SRAM
A 100-pin, 7.5ns, 32K x 32 Micron Synchronous Burst SRAM (U11) is used for Processor/Local Bus data
storage on the RDK. During Direct Slave memory burst cycles, the SBSRAM performs continuous back-
to-back single read cycles or single write cycles. The Xilinx CPLD SBSRAM controller (U10) does all of
the timing conversion and generates the lower 8 address bits to the SBSRAM. The SBSRAM takes 7
upper address lines (LA16-LA10) directly from the PEX 8311 and 8 lower address lines (MA[9:2]) from
the SBSRAM controller. The data lines of the SBSRAM are directly connected to the PEX 8311 local data
bus (LD31-LD0).
3.3.3 Xilinx CPLD
A 5ns Xilinx XC9572XL-5TQ100C CPLD (U10) is used as the SBSRAM controller, external
Processor/Local Bus arbiter, and chip select generator.
The SBSRAM controller in the CPLD generates the lower 8-bit memory address (MA[9:2]), SBSRAM chip
select (SRAMCS#), SBSRAM output enable (SRAMOE#), and SBSRAM byte write enables
(SRAM_BW_[3:0]) to the SBSRAM. It latches the starting address signals (LA[9:2] for C mode and
LAD[9:2] for J mode), and uses its built-in internal address counter to advance the addresses to the
SBSRAM. The SBSRAM controller also generates the active low ready signal (READY#) to terminate
normal PEX 8311 memory cycles and also generates the active low (BTERM#) input to the PEX 8311 to
break the continuous burst memory cycle when its internal address counter reaches the final count (FFh).
The external Processor/Local Bus arbiter in the CPLD accepts the Processor/Local Bus request signals
(LBR [1:0]) from Processor/Local Bus masters, if there are any, and the bus request from the PEX 8311
(LHOLD). It generates bus grant signals LBG [1:0] to the Processor/Local Bus masters and LHOLDA to
the PEX 8311.
The chip select generator in the CPLD generates the SBSRAM chip select (SRAMCS#) and four
additional active low chip selects for the Processor/Local Bus devices. The chip select signals are
partially decoded from the upper four address lines (LA31-LA28) on the Processor/Local Bus. They can
be re-programmed by altering the CPLD Verilog code.
3.3.4 Internal Clock
The PEX 8311 requires an internal clock source in addition to the PCI Express clock and the local clock.
When the PEX 8311 is operating in Endpoint mode the PEX 8311 will generate the internal clock itself.
The internal clock output (CLKOUT, ball A8) is fed directly to the internal clock input (CLKIN, ball A15) via
the 0 ohm series resistor R53.
When the PEX 8311 is operating in Root Complex mode then the internal clock must be provided from an
external source. While the PEX 8311RDK is not designed to operate in Root Complex mode provision
has been made for an external clock oscillator to provide the internal clock to the PEX 8311. The
components for the external clock are not assembled nor do they appear on the BOM. Customers who
require this feature must source and assemble the components themselves. PLX takes no responsibility
for boards damaged during this operation
If the external oscillator is to be used remove R53 and assemble R52, R150, C96, C97 and U13. The
maximum operating frequency for U13 should be 66MHz.